The front-end synthesis of analog circuits has been a long-standing challenge since the advent of integrated circuits. Many methods, ranging from conventional optimization-based techniques to emerging learning-based approaches, have been extensively explored to address this challenge. Yet, these methods are data-driven and often suffer from low design efficiency, due to their heavy reliance on time-consuming circuit simulators, which are frequently used in the synthesis loop for real-time evaluation of the evolving circuit design. In addition, benchmarking these methods is also largely unachievable due to their exclusive use of commercial semiconductor technology for evaluation. This “Late Breaking Results” introduces Opera, an open and efficient platform for the data-driven synthesis of analog circuits. Specifically, Opera develops efficient surrogate models for various circuits and integrates them into open-source OpenAI Gym-like environments to enable efficient synthesis. Case studies on exemplary circuits show that this platform can accelerate the conventional data-driven synthesis flow by up to $40 \times$. It also enables the benchmarking of various synthesis methods with standardized environments built upon an open-source semiconductor process.

Compute-In-memory (CIM) has shown significant potential in efficiently accelerating deep neural networks (DNNs) at the edge, particularly in speeding up quantized models for inference applications. Recently, there has been growing interest in developing floating-point-based CIM macros to improve the accuracy of high-precision DNN models, including both inference and training tasks. Yet, current implementations rely primarily on digital methods, leading to substantial power consumption. This paper introduces a hybrid domain CIM architecture that integrates analog and digital CIM within the same memory cell to efficiently accelerate high-precision DNNs. Specifically, we develop area-efficient circuits and energy-efficient analog-to-digital conversion techniques to realize this architecture. Comprehensive circuit-level simulations reveal the notable energy efficiency and lossless accuracy of the proposed design on benchmarks.

Integrating deep learning with ubiquitous image sensors has empowered various edge vision applications such as classification, segmentation, and detection. Deploying these data-driven applications requires holistic optimizations, from front-end sensing to back-end processing, within the limited resources of edge devices. While significant advances have been made in the efficient processing of sensory data in the back end with optimizations of learning algorithms (e.g., compression) and development of computing hardware (e.g., accelerators), the energy efficiency of front-end sensors remains significantly limited due to conventional high-fidelity image acquisition and the resulting massive off-chip data transfer.This paper proposes a domain-specific visual acquisition method, LoRASensE, learnable low-rank acquisition in sensors tailored for efficient data-driven edge vision applications. LoRASensE is an algorithm-hardware co-design framework that integrates a learned low-rank compressor into image sensors to acquire compressed features. Specifically, this compressor is optimized alongside downstream vision tasks to ensure end-to-end accuracy and is implemented with efficient analog processing hardware. Our extensive evaluations on real-world datasets across various vision applications demonstrate that LoRASensE can achieve a 12.5× compression ratio with a just 1-b compressor, minimal accuracy loss, and 86.9% energy saving compared to the conventional high-fidelity acquisition. Multi-dimensional comparisons further show that LoRASensE also significantly outperforms existing in-sensor compression methods.