Modern societies increasingly rely on interconnected devices and individuals for information exchange and monitoring. In this manner, drones, as flying smart nodes in the wireless network ecosystem, facilitate diverse applications, such as industrial, civilian, and disaster response operations. However, the widespread adoption of drone networks introduces significant challenges regarding interoperability, privacy, and security. Advances in quantum computing exacerbate these issues by rendering classical cryptographic measures inadequate, necessitating the adoption of quantum-safe approaches. Existing solutions fail to address all potential threats or lack post-quantum security. This work sets out to propose a robust lattice-based authentication and communication protocol for drone networks, addressing these challenges. The protocol integrates dynamic credentials, timestamps, multi-factor authentication, and context information to enhance security. The scheme's security is analyzed using the DY and BPR models and formally verified via the AVISPA tool. Performance evaluations and comparisons with existing solutions demonstrate the protocol's functionality, showcasing a reasonable trade-off between security and performance. By leveraging modern cryptographic techniques, the proposed scheme ensures reliable and robust drone operations, effectively mitigating various attacks beyond session establishment while safeguarding privacy, and supporting dynamic network events.

The elliptic curve digital signature algorithm (ECDSA) is widely used for guaranteeing data integrity and user authentication in internet of things (IoT) applications such as intelligent transport systems (ITS). In ITS, vehicles, infrastructures, and data networks communicate using vehicle-to-everything (V2X) protocols. In V2X message broadcasting, the ECDSA guarantees data security and privacy. During traffic congestion, the signature generation/verification latency becomes crucial. Hence, this paper proposes a high-throughput and efficient ECDSA architecture for vehicle-to-vehicle (V2V) applications. We investigate the double point multiplication (DPM) method for reducing computational overhead and propose a new finite field multiplier architecture for latency improvement. Our implementation results over$p_{256}$on Virtex-7 field programmable gate array (FPGA) show that our design’s throughput and efficiency are improved compared to previous works by at least$4.9\times $and$7.2\times $, respectively. This unit generates a signature in$167 {\mathrm {\mu \text { s} }}$and verifies a message in$188 {\mathrm {\mu \text { s} }}$. Also, our application-specific integrated circuit (ASIC) synthesis on$45 {\mathrm { \text {n} \text { m} }}$and$180 {\mathrm { \text {n} \text { m} }}$technologies can verify 4416 messages per second by consuming$1.3 {\mathrm {\mu \text { J} }}$and$9.4 {\mathrm {\mu \text { J} }}$energy, respectively. This advantage makes the design affordable for other IoT applications.

We present a pipelined Montgomery multiplier tailored for SIKE primes. The latency of this multiplier is far shorter than that of the previous work while its frequency competes with the highest-rated ones. The implementation results on a Virtex-7 FPGA show that this multiplier improves the time, the area-time product (AT), and the throughput of computing modular multiplication by at least 2.30, 1.60, and 1.36 times over SIKE primes respectively. We have also developed a CPU-like architecture to perform SIDH and SIKE using several instances of our modular multiplier. Using four multipliers on a Virtex-7 FPGA, the encapsulation and the decapsulation of SIKE can be performed at least 1.45 times faster while improving the AT by at least 1.35 times over all SIKE primes. We have also evaluated our implementation on two other FPGAs. The implementation on Artix-7 improves the time and the AT of performing these two steps of SIKE by at least 1.90 and 1.80 times, respectively. On Kintex UltraScale+, these improvement factors are 2.05 and 2.08, respectively. On this device, these two steps take 3.11, 3.52, 4.66, and 6.59 milliseconds on$p_{434}$,$p_{503}$,$p_{610}$, and$p_{751}$, respectively.

Public key cryptography lies among the most important bases of security protocols. The classic instances of these cryptosystems are no longer secure when a large-scale quantum computer emerges. These cryptosystems must be replaced by post-quantum ones, such as isogeny-based cryptographic schemes. Supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE) are two of the most important such schemes. To improve the performance of these protocols, we have designed several modular multipliers. These multipliers have been implemented for all the prime fields used in SIKE round 3, on a Virtex-7 FPGA, showing a time and area-time product improvement of up to 60.1% and 64.5%, respectively. These multipliers are also suitable for applications such as RSA, as shown by implementations for 512-bit, 1024-bit, and 2048-bit generic moduli on a Virtex-7 FPGA. Our fastest multiplier has been used in the implementation of SIDH and SIKE round 3. Employing six instances of this multiplier, SIDH completes after 7.33, 8.93, 13.39, and 18.67 milliseconds and the encapsulation and the decapsulation of SIKE is performed in 7.13, 8.68, 13.08, and 18.16 milliseconds over p434, p503, p610, p751, respectively, which yields a least improvement factor of 1.23.

By exponential increase in applications of the Internet of Things (IoT), such as smart ecosystems or e-health, more security threats have been introduced. In order to resist known attacks for IoT networks, multiple security protocols must be established among nodes. Thus, IoT devices are required to execute various cryptographic operations, such as public key encryption/decryption. However, classic public key cryptosystems, such as Rivest-Shammir-Adlemon and elliptic curve cryptography are computationally more complex to be efficiently implemented on IoT devices and are vulnerable regarding quantum attacks. Therefore, after complete development of quantum computing, these cryptosystems will not be secure and practical. In this paper, we propose InvRBLWE, an optimized variant for binary learning with errors over the ring (Ring-LWE) scheme that is proven to be secure against quantum attacks and is highly efficient for hardware implementations. We propose two architectures for InvRBLWE: 1) a high-speed architecture targeting edge and powerful IoT devices and 2) an ultralightweight architecture, which can be implemented on resource-constrained nodes in IoT. The proposed architectures are scalable regarding security levels and we provide experimental results for two versions of the InvRBLWE scheme providing 84 and 190 bits of classic security. Our implementation results on field programmable gate array dominate the best of the classic and post-quantum previous implementations. Moreover, our two different application specific integrated circuit (ASIC) implementations show improvement in terms of speed, area, power, and/or energy. To the best of our knowledge, we are the first to implement learning with error-based cryptosystems on ASIC platform.