As an alternative to bulk FinFET, nanosheet (NS) FETs have been proposed to suppress short-channel effects (SCEs) in sub 3-nm device technology. While NS FETs effectively reduce off-state current (IOFF), boosting on-state current (ION) remains challenging due to process difficulties. In this paper, we introduce a novel V-Notch-shaped source/drain metal contact design for NS FETs. This design significantly increases the metal-semiconductor contact area (AC), thereby reducing the contact resistance (RC), as well as the source and drain resistances (RSandRD) by 42.3 % and 64.4 %, respectively. As a result, the proposed V-Notch contact design improvesIONand reduces RC delay by 6.37 % and 5.37 %, respectively, thereby enhancing chip-level performance. Moreover, it presents a practical structural modification strategy for advanced NS FET technologies without requiring changes to the design rules or adding complexity to the fabrication process.

This paper presents a neural recording integrated circuit (IC) with a DC-coupled VCO-based continuous-time ΔΣ modulator with a novel input transistor ΔΣ digital-to-analog converter (DAC) technique. The input transistor operating as a transconductor is implemented in the form of a transistor DAC (TR-DAC) consisting of multiple transistors, which enables the ΔΣ operation according to the output digital code. Notably, this topology isolates the input from the feedback loop, resulting in exceptionally high input impedance. Furthermore, the input transistor itself functions as a ΔΣ DAC, eliminating the need for additional passive or active DAC components. Consequently, the proposed design significantly reduces area consumption, enabling its application to future scalable brain-machine-interface (BMI) systems. The proposed IC designed in a 0.18-µm CMOS process consumes only 4.7 µW with a bandwidth of 5.12 kHz. Thanks to its DC-coupling characteristics and small input parasitic capacitance, the design achieves a high input impedance of 1.26 GΩ. Furthermore, the chip occupies a compact area of 0.054 mm2per channel, while the input TR-DAC used as a ΔΣ DAC occupies only 0.008 mm2.

A super-high-resolution capacitance-to-digital converter (CDC) capable of reaching sub-aF capacitance resolution has been proposed. The CDC employs a continuous-time (CT) low-noise capacitance-to-voltage converter (CVC) followed by a high linearity bandpass$\Delta\Sigma$ADC$(\text{BP}-\Delta\Sigma \mathrm{M})$without frequency demodulation. By avoiding demodulation and utilizing a narrow-band sensing technique, the proposed CDC achieves a sub-aF capacitance resolution while expanding the input capacitance range through a coarse C-DAC calibration loop. The proposed circuit has been implemented in a$0.35-\mu \mathrm{m}$CMOS process with a 3.3 V power supply voltage. The CDC shows a capacitance resolution of 0.98$\text{aF}_{\text{rms}}$, with a capacitance range of 3.1 pF, while consuming 4.16 mW.

This paper presents a galvanic coupling communication (GCC) receiver for bionic arms. The detachability of the bionic arms results in various changes such as contact impedance variation and electrode misalignment. Its dynamic usage conditions may lead to contact with metallic objects. Moreover, the GCC has an inherent drawback of narrow channel bandwidth, which limits the communication speed. In this work, we demonstrate that the GCC can offer robust operation under varying channel conditions by using HFSS simulations. In addition, by applying a cascaded continuous-time linear equalizer, the proposed receiver widens the bandwidth from 1 MHz to 60 MHz. Implemented in 0.18-um CMOS process, a 30-Mbps GCC receiver operates successfully for bionic arms with robustness against channel condition variations while following body safety guidelines and consuming 650 uW.