This paper proposes convergence enhancement to state-space averaging (SSA) methodology for steady-state and small-signal analysis of high-ratio hybrid DC-DC converters, first using analysis of Double-Step-Down (DSD) topology, including parasitics, as an example, then extending to other hybrid topologies with different numbers of capacitors and inductors. The enhanced SSA method can be used to:1)derive small-signal control-to-output transfer functions, which is essential to optimize the compensator for fast and stable closed-loop operation;2)calculate steady-state inductor currents, output voltage, input current and the voltage(s) across the flying capacitor(s),$V_{CFs}$, which is important to determine steady-state characteristics and performance;3)include circuit non-idealities such as parasitics and timing mismatches; and4)evaluate$V_{CF}$balancing property by the proposed matrix invertibility principle and added constants, and determine whether dedicated$V_{CF}$balancing circuits can be eliminated, which is considered an important benefit with reduced complexity and improved reliability. The theoretical results of DSD are then plotted in MATLAB and verified in simulations using PSIM and Cadence periodic transfer function (PXF) analysis, and measurement results using GaN devices. The simulation and measurement results match well with theoretical analysis. The enhancement is then extended beyond the DSD topology to analyze emerging hybrid topologies with more switched inductors and capacitors, future-proofing its capability to be applicable to new hybrid topologies.

This paper introduces a single-inductor 4-phase hybrid switched-capacitor (4PSC) topology for integrated high-ratio direct down conversion suitable for point-of-load applications. The proposed topology consists of a 3-phase 4:1 switched-capacitor stage, reducing the switching node swing to 12-V (1/4 of the input) to significantly reduce switching loss, and an inductor to softly charge and discharge the flying capacitors with an extra phase (hence 4-phase operation) with controlled duty cycle to regulate the output voltage to 1V for direct-down conversion. The converter operates with a 4X effective switching frequency, which reduces the ripple/inductance required or switching frequency for better efficiency. With the same output voltage ripples as double step-down (DSD) and 3-level (3L1P) buck converters, the on-time is 4X that of DSD and 3L1P converters, which reduces the challenges in controller design. Lower-voltage (LV) transistors, such as 12-V devices, can be used in some of the switches to significantly improve efficiency. When compared to DSD and 3-Level converters that are state-of-the-art integrated topologies, with the same inductor, output capacitor, and output ripples in the same BCD process, this design achieves: 1) an efficiency comparable or higher than DSD (e.g., ∼3% higher at 48V-1V/5A); 2) along with using only one inductor instead of two for DSD, which can reduce the cost and increase the power density; and 3) much higher efficiency compared to a 3-level buck converter. The 4PSC topology is verified in simulations, showing peak efficiencies of ∼85% and ∼91% in a 180-nm BCD process with 48V-1V and 48V-2V conversions, respectively.

Diagnostic testing plays an important role in modern medicine, helping physicians make informed decisions regarding disease diagnosis and treatment. Proteins’ biomarkers are utilized to detect disease onset, progression, efficacy of medicines, and patient susceptibility to get a specific kind of disease. Electrochemical impedance spectroscopy (EIS) is likely to underpin the progressive drive toward sensitive, miniaturized, and portable biomarker detection practices. The EIS is a highly sensitive detection method adopted to find the electrical response of chemical samples by applying low amplitude ac voltages/currents with tunable frequency. Conventional EIS systems use mixers and lock-in amplifiers to find both the real and imaginary components of the complex impedance. In this article, we present a partially integrated EIS measurement system to find the impedance of a biological sample. It includes a programmable sine-wave synthesizer (SWS) block with a frequency range of$500 \mu $Hz to 100 kHz. The implementation is based on switched-capacitor filters that adjust the cutoff frequency by changing the clock. The sample impedance is measured through mostly digital magnitude and phase-detection blocks. The proposed EIS system is realized using a 0.18-$\mu \text{m}$technology with a 0.35-mm2 active area and 380-$\mu \text{W}$power consumption. The proposed magnitude detection archives a differential nonlinearity (DNL) performance of −0.34/+0.3 LSB and an integral nonlinearity (INL) of −0.75/+2 LSB. The system is used to measure the impedance of biological samples containing tumor necrosis factor alpha (TNF-$\alpha$) protein at variable concentrations.

Electrical impedance spectroscopy (EIS) is a powerful technology for accurate disease detection at the point- of-care (POC) from biosensors. Nevertheless, EIS usually involves lock-in amplifiers and mixers to detect both the magnitude and phase of the complex impedances. This paper presents a highly digital impedance measurement system-on- chip, which can convert the magnitude and phase of impedance to 10-bits digital codes integrated with a filter-based wide-range programmable sinusoidal wave synthesizer (SWS). The proposed SWS utilizes switched-capacitor circuits such that the corner frequency can be adjusted by changing its switching frequency. The proposed EIS system was fabricated using a 180nm process with an active area of only 0.35 mm2. The SWS generates output frequency in the range of 579 μΗζ-48.9 kHz with measured total harmonic distortion of 0.152% at 100 Hz and 0.116% at 10 kHz. The DNL of the proposed magnitude converter is within -0.34/+0.3 LSB and the INL is around -0.75/+2 LSB. To validate the function of the proposed EIS measurement system, it is utilized to detect the tumor necrosis factor α in biological samples.