This paper presents a high-throughput impedance readout IC with a novel synchronous cyclic integration technique using a scalable capacitive transimpedance stage. The proposed technique removes the need for the low pass filter (LPF) in the readout chain and performs the I/Q demodulation within a single cycle. Fabricated in a 180-nm CMOS process, the proposed IC consumes 50 μW from a 1.2-V supply. It can measure impedances over a frequency of 100 Hz to 100 kHz with an accuracy of 99.7% and can achieve a throughput of 50 kSps at 100 kHz input frequency.

This paper presents a low-noise, low-power biopotential recording IC with programmable gain and a reconfigurable number of channels. The analog front end (AFE) with tunable gain from 20 dB to 54 dB can select the number of channels and combination of channels for reconfigurable signal acquisition capability. The proposed hybrid DC-servo loop is employed for fast electrode DC offset (EDO) cancellation up to 240 mV within 10 ms. Designed in a 0.18-μm CMOS process, the proposed IC achieves input-referred noise (IRN) of 1.12 μVrms at the highest gain mode. The overall system achieves 66.35-dB SNDR with the successive approximation register (SAR) analogto-digital converter (ADC) and consumes 5.74 μW with 0.40 mm2 area per channel.

This paper presents a ΔΣ-modulator-based reconfigurable multimodal sensor interface integrated circuit (IC), offering a novel approach to the multimodal measurement of voltage, capacitive, and current signals. A direct-conversion structure is employed in the multimodal sensor interface, and its reconfigurable ΔΣ modulation scheme ensures compact die area, high energy efficiency, and enhanced dynamic range. Fabricated in a 180-nm CMOS process, the multimodal sensor interface achieves measured dynamic ranges of 70.6 dB, 97.8 dB, and 60.0 dB for voltage, capacitance, and current modes, with measured power consumptions of 22.2 μW, 23.0 μW, and 37.7 μW, respectively. The proposed system demonstrates significant improvements in the dynamic range relative to power consumption compared to other state-of-the-art multimodal sensor interface IC designs.

This paper presents a neural recording integrated circuit (IC) with a DC-coupled VCO-based continuous-time ΔΣ modulator with a novel input transistor ΔΣ digital-to-analog converter (DAC) technique. The input transistor operating as a transconductor is implemented in the form of a transistor DAC (TR-DAC) consisting of multiple transistors, which enables the ΔΣ operation according to the output digital code. Notably, this topology isolates the input from the feedback loop, resulting in exceptionally high input impedance. Furthermore, the input transistor itself functions as a ΔΣ DAC, eliminating the need for additional passive or active DAC components. Consequently, the proposed design significantly reduces area consumption, enabling its application to future scalable brain-machine-interface (BMI) systems. The proposed IC designed in a 0.18-µm CMOS process consumes only 4.7 µW with a bandwidth of 5.12 kHz. Thanks to its DC-coupling characteristics and small input parasitic capacitance, the design achieves a high input impedance of 1.26 GΩ. Furthermore, the chip occupies a compact area of 0.054 mm2per channel, while the input TR-DAC used as a ΔΣ DAC occupies only 0.008 mm2.

This paper presents a novel high-throughput impedance measurement integrated circuit (IC) with baseline cancellation for neural EIT applications. The proposed technique uses a peak detector to obtain impedance magnitude every cycle. After taking the peak, the peak detector is reset to a DC baseline voltage. And, the signal swinging between the amplitude and the reset baseline is further amplified, allowing to measure small impedance variations even with a large baseline. The proposed IC fabricated in a 180-nm standard CMOS process can measure impedance variations of >0.1% baseline can be measured, while achieving high throughput of 100 kS/s at 100 kHz input frequency. Scalable design allows the proposed IC to support a wide frequency range from 100 Hz to 100 kHz with a power consumption from 31 μW to 39 μW from a 1.2-V supply.

A super-high-resolution capacitance-to-digital converter (CDC) capable of reaching sub-aF capacitance resolution has been proposed. The CDC employs a continuous-time (CT) low-noise capacitance-to-voltage converter (CVC) followed by a high linearity bandpass$\Delta\Sigma$ADC$(\text{BP}-\Delta\Sigma \mathrm{M})$without frequency demodulation. By avoiding demodulation and utilizing a narrow-band sensing technique, the proposed CDC achieves a sub-aF capacitance resolution while expanding the input capacitance range through a coarse C-DAC calibration loop. The proposed circuit has been implemented in a$0.35-\mu \mathrm{m}$CMOS process with a 3.3 V power supply voltage. The CDC shows a capacitance resolution of 0.98$\text{aF}_{\text{rms}}$, with a capacitance range of 3.1 pF, while consuming 4.16 mW.