This paper presents a system-on-chip (SoC) architecture for an active implantable microsystem that combines electrical recording with optogenetic stimulation for closed-loop neuromodulation. The SoC is designed to support a 4-shank optrode (opto-electrode) fork with 8 differential recording channels (0.1-5000Hz bandwidth, 10mVpp range, 12-bit resolution) to observe neural signals on electrodes and 32 driver circuits (2mA range, 6-bit current resolution with μs timing resolution) for microLED optical stimulation. Each SoC additionally integrates diagnostic instrumentation to measure electrical resistance across any of its I/O lines. The SoC features a custom 4-wire interface that provides power and data communication across multiple chips using a shared bus allowing for multiple forks to be stacked to form two dimensional optrode arrays. Each chip has an independent controller that receives, interprets and executes commands, and can transmit neural data while simultaneously controlling LED outputs. The circuit is implemented in a 180nm CMOS process, with each chip occupying a 5mm×2.45mm silicon footprint, designed specifically to mount on the base of the silicon optrode fork.

Memristors have emerged as promising candidates for multilevel data storage, in-memory processing, and neural networks since their intrinsic programmability of resistance states under applied stimuli has been well revealed in memristor modeling. However, the programming uncertainty arising from the inherently stochastic nature of the device itself has been overlooked in previous modeling approaches. This omission hinders the incorporation of memristor stochasticity into time-domain circuit simulation. To address this issue, we propose a behavior model that incorporates real-time programming stochasticity. Our model stands out for several attributes: 1) programming stochasticity is included and exhibited in its resistance change over time; 2) its stochastic behavior is depicted by the summation of its deterministic behaviors and a noise signal; and 3) both deterministic behaviors and noise amplitudes depending on the pulse amplitude v and the memristor resistance R are determined by sufficient characterization data of our in-house TiO2 devices in a data-driven method. Consequently, our model is validated as highly matched to the characterized memristor device in terms of time-domain resistance evolution. Additionally, the modeling process can be adapted to different memristors with significant device variations. Furthermore, the model is transformed into the standard Verilog-A style for in-circuit simulation. To demonstrate its compatibility with system-level circuit simulation, a mixed-signal CMOS circuit is designed. This circuit explores the feasibility of storing multibit data within a single memristor, while considering its stochasticity.

Emerging resistive technologies include several nonlinear devices with the capability of changing their resistive state based on the voltage (/current) across (/flowing through) the device. The state of these devices is typically read by applying a small DC voltage across the DUT and measuring the current flowing through it (or vice-versa). However, given their non-linear behaviour, a change in voltage across the device, albeit small, will result in a change in the measured resistance. This is undesirable when characterising these devices, as voltage drops due to metal routing or switches in the signal path will affect the measured resistance. This work puts forward the idea of closing the loop by sensing the voltage across the DUT through a Kelvin connection, and then making adjustments to the line voltage to compensate for any voltage drop. This in turn enables larger arrays, and a higher number of states to be read because of the increased precision. An on-chip CMOS design is proposed through the use of a dual-input-pair amplifier. The resulting system is capable of driving a load between 1 kΩ and 10 MΩ with a settling time less than 1 µs for a DUT read voltage of 0.5 V.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

A number of recent and current efforts in brain machine interfaces are developing millimetre-sized wireless implants that achieve scalability in the number of recording channels by deploying a distributed 'swarm' of devices. This trend poses two key challenges for the wireless power transfer: (1) the system as a whole needs to provide sufficient power to all devices regardless of their position and orientation; (2) each device needs to maintain a stable supply voltage autonomously. This work proposes two novel strategies towards addressing these challenges: a scalable resonator array to enhance inductive networks; and a self-regulated power management circuit for use in each independent mm-scale wireless device. The proposed passive 2-tier resonant array is shown to achieve an 13.5% average power transfer efficiency, with ultra-low variability of 1.77% across the network. The self-regulated power management unit then monitors and autonomously adjusts the supply voltage of each device to lie in the range between 1.7V-1.9V, providing both low-voltage and over-voltage protection.

Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency when observing neural activity over a long period of time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing local field potentials (LFPs) only, chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a ΔΣ based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μm CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.77μVrms. The resulting electronics has a core area of 2.1 mm2and a power budget of 92 μW