Weiqing Ji

dblp:224/5700 · DBLP profile ↗
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15ranked-venue papers
6as first author
11since 2021 · last 2026
—ORCID · conflict

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Systems, architecture and hardware · 15 · 6 first-author · 11 since 2021
YearPublicationVenuePosition
2026 SWIPER: A Sliding-Window-Based Progressive ILP for Scalable Escape Routing of Chiplet Interconnects
abstract
Facing the complexity of escape routing in high-density interconnects within chiplet systems, conventional methods often struggle to balance efficiency and quality under large-scale design scenarios. This paper presents a Sliding-Window-based progressive Integer linear Programming (ILP) for scalable Escape Routing of chiplet interconnects, called SWIPER, which maintains high routing quality with controllable complexity by sequentially optimizing localized subproblems. Our approach uses predefined geometric patterns to adaptively select single- or multi-layer paths using ILP model, to avoid routing conflicts, thereby improving routing flexibility. Experimental results demonstrate that, compared with existing methods, SWIPER improves the routing completion rate by up to 28% in obstacle-dense scenarios, reduces the number of vias by up to 18%, and reduces the wirelength by up to 1.5%, exhibiting excellent scalability and practical robustness.
Ningkang Hao, Haochang Tian, Yue Li 0035, Weiqing Ji, Hailong Yao 0002
ACM Great Lakes Symposium on VLSI5
2026 CERT: A Curved Escape Routing Framework for High-Speed Differential Pairs in Dense BGA Packages
abstract
With the rapid advancement of 5G communication, AI accelerators, and high-performance computing (HPC) systems, the data rate of BGA differential signals has surpassed 56Gbps. Traditional 45° routing causes impedance discontinuity and EMI issues, while also triggering design rule violations (DRVs) with route-keepout areas in dense BGA packages. In contrast, curved routing can provide superior signal integrity (SI), but relies on labor-intensive manual design. To address the above issues, this paper proposes CERT, a novel smooth (tangent-continuous) curved escape routing framework for high-speed differential pairs in dense BGA packages. A tailored hexagonal graph model with polyline-to-arc conversion rules is proposed, which guarantees the tangent continuity of curved wires for differential pairs and enables the direct reuse of traditional polyline escape routing algorithms. Experiments show CERT completes routing of the industrial benchmark in 2s (vs. 1 week for manual routing). To the best of our knowledge, this is the first automatic curved escape routing work for differential signals with route-keepout area adaptability.
Weiqing Ji, Boxuan Xu, Hongli Dai, Chaojie Liu, Mingyang Kou, Hailong Yao 0002
ACM Great Lakes Symposium on VLSI1
2026 Integrated Track Assignment and Detailed Routing for Enhanced Triple Patterning Lithography
abstract
As semiconductor manufacturing advances toward smaller technology nodes, triple-patterning lithography (TPL) has become indispensable. Existing TPL-aware routers address manufacturability constraints too late, leading to numerous stitches, conflicts, and mask density imbalances. To overcome this, we propose a "shift-TPL-left" strategy that, for the first time, integrates TPL awareness into the track assignment (TA) stage and tightly coordinates it with detailed routing (DR). This approach guides the TPL-aware detailed routing from a more macroscopic level, resulting in faster convergence and fewer DRC violations. Experimental results demonstrate that our method achieves DRC clean in 80% of cases on the ISPD’18 dataset, outperforms the state-of-the-art TPL-aware routing method by 7 × in mask balance score, and achieves a 6 × speedup in runtime.
Chengkai Wang, Weiqing Ji, Mingyang Kou, Nengyong Zhu, Hailong Yao 0002
ACM Great Lakes Symposium on VLSI2
2025 GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
abstract
Coarse-grained reconfigurable architecture (CGRA) has emerged as a promising solution for accelerating computationally intensive applications, particularly in the field of artificial intelligence. One of the primary challenges for CGRA compilers is generating effective mapping results for complex applications within a limited time-frame. This paper presents an enhanced pre-scheduling method that integrates Integer Linear Programming (ILP) and Graph Neural Networks (GNN), along with a corresponding two-stage mapping approach. This combination significantly reduces the search space and accelerates the solution process for mapping problems. Experimental results demonstrate performance improvements ranging from $29.4 \%$ to $406.7 \%$, along with compilation time reductions of up to $1106.8 \times$ compared to existing compilation techniques, as well as excellent scalability.
Mingyang Kou, Weiqing Ji, Shouyi Yin, Hailong Yao 0002
DAC2
2025 Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography
abstract
Triple patterning lithography (TPL) has been recognized as one of the most promising solutions to print critical features in advanced technology nodes. A critical challenge within TPL is the effective assignment of the layout to masks. Recently, various layout decomposition methods and TPL-aware routing methods have been proposed to consider TPL. However, these methods typically result in numerous conflicts and stitches, and are mainly designed for 2-pin nets. This paper proposes a multipin net routing method in triple patterning lithography, called Mr.TPL. Experimental results demonstrate that Mr.TPL reduces color conflicts by 81.17%, decreases stitches by 76.89%, and achieves up to $5.4 \times$ speed improvement compared to the state-of-the-art TPL-aware routing method.
Chengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen 0006, Nengyong Zhu, Hailong Yao 0002
DAC2
2025 VAER: Via-Aware Escape Routing for Chiplet Interconnection
Haochang Tian, Weiqing Ji, Mingyang Kou, Chengkai Wang, Hailong Yao 0002
ACM Great Lakes Symposium on VLSI2
2025 NaviMap: Partial Order-Guided Neural Architecture via Deep Q-Networks for Efficient CGRA Mapping
abstract
Coarse-Grained Reconfigurable Architectures (CGRAs) have emerged as promising solutions for energyefficient computing in edge devices and datacenter accelerators. While offering substantial performance benefits, their adoption is hindered by the NP-hard loop mapping problem during compilation. In this paper, we present NaviMap, a neuralsymbolic framework combining partial order-aware graph embeddings with deep reinforcement learning. Experimental results demonstrate that NaviMap achieves a$1.95 \times$speedup in solving CGRA mapping problems compared with state-of-the-art methods, while producing mappings with equivalent or superior performance.
Mingyang Kou, Jun Zeng 0001, Xinyu Peng, Weiqing Ji, Hailong Yao 0002
ICCD4
2023 GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates
abstract
Microfluidic biochips have emerged with significant promise and versatility in automating a variety of biochemical protocols. Accurate preparation of fluid samples with microfluidic mixers is an essential component of these protocols, where concentration prediction and generation are critical. Recently, machine learning models have been adopted in concentration prediction, which demonstrate great potential in enhancing the efficiency and scalability over the traditional finite element analysis (FEA) methods. However, the state-of-the-art machine learning-based method can only predict the concentration of microfluidic mixers with fixed input flow rates, but suffers poor prediction accuracy for multiple input flow rates. To address this issue, this paper proposes a new concentration prediction method based on the graph attention networks (GAT). By modeling each channel of the mixer as a graph node in a GAT, the proposed method efficiently and accurately predicts the generated concentration of random microfluidic mixers with multiple input flow rates. Experimental results show that compared with the state-of-the-art method, the proposed GAT-based simulation method obtains a reduction of 85% in terms of errors of predicted concentration, which validates the effectiveness of the proposed GAT model.
Weiqing Ji, Hailong Yao 0002, Tsung-Yi Ho, Ulf Schlichtmann
ACM Great Lakes Symposium on VLSI1
2023 SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips
abstract
In paper-based digital microfluidic biochips (P-DMFBs), conductive electrodes and control lines are printed on the same side of the photo paper, which introduces a critical design challenge on the so-called control interference issue. This introduces a distinct escape routing problem, named Self-Obstacle Avoiding Escape Routing (SOAER). In the SOAER problem, each electrode has a specific set of routing obstacles of its own, which are forbidden to be crossed over by the control line of the electrode. Based on an enhanced network flow model, this paper proposes an effective SOAER routing method for P-DMFBs. Experimental results show that compared with the state-of-the-art method, SOAER obtains 49x speedup in runtime. Our proposed method also shows the efficiency and effectiveness of the overall system. The success rate is up to 100% and the runtime is decreased significantly.
Weiqing Ji, Xingcheng Yao, Hailong Yao 0002, Tsung-Yi Ho, Ulf Schlichtmann
ACM Great Lakes Symposium on VLSI1
2022 GNN-based concentration prediction for random microfluidic mixers
abstract
Recent years have witnessed significant advances brought by microfluidic biochips in automating biochemical processing. Accurate preparation of fluid samples with microfluidic mixers is a fundamental step in various biomedical applications, where concentration prediction and generation are critical. Finite element analysis (FEA) is the most commonly used simulation method for accurate concentration prediction of a given biochip design, such as COMSOL. However, the FEA simulation process is time-consuming with poor scalability for large biochip sizes. This paper proposes a new concentration prediction method based on the graph neural networks (GNN), which efficiently and accurately predicts the generated concentration by random microfluidic mixers of different sizes. Experimental results show that compared with the state-of-the-art method, the proposed GNN-based simulation method obtains a reduction of 88% in terms of errors of predicted concentration, which validates the effectiveness of the proposed GNN model.
Weiqing Ji, Xingzhuo Guo, Shouan Pan, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao 0002
DAC1
2021 Machine Learning Based Acceleration Method for Ordered Escape Routing
abstract
Escape routing, especially ordered escape routing, is a critical design stage for both printed circuit boards (PCBs) and integrated fan-out (InFO) wafer-level chip-scale packages. Previous works formulate ordered escape routing as boolean satisfiability (SAT) or integer linear programming (ILP) problems. Although optimal routing solutions can be obtained by above-mentioned approaches, the runtime is unacceptable for large-scale designs due to the exponential time complexity of SAT and ILP solvers. In this paper, we first attempt to address ordered escape routing problems with machine learning. We propose a learning-based method to accelerate existing solvers by reducing the solution space of the original problem. The proposed method is flexible, which can be combined with different ordered escape routing algorithms. Specifically, a fully convolutional neural network is trained to predict the probability of each routing grid to be occupied by routing paths. Thus, routing grids with low-probability usage can be removed to reduce the solution space. Experimental results show that the proposed method is effective for both SAT and ILP solvers of ordered escape routing. It achieves an acceleration of 4∼ 370x on average, with a slight increase in the total wirelength. Also, our model has a strong generalization ability. Although it is trained on $10\times 10$ pin array problems, it works well on larger problem sizes such as 14 x 14.
Zhiyang Chen 0006, Weiqing Ji, Yihao Peng, Datao Chen, Hailong Yao 0002
ACM Great Lakes Symposium on VLSI2
2020 Transfer Learning-Based Microfluidic Design System for Concentration Generation∗
abstract
Due to the complexity of human physiology and variability among individuals, e.g., genes, environment, lifestyle exposures, etc., personalized medicine has attracted great interest in the past few years. For synthesizing personalized medicine, it is critical to prepare customized samples with specific concentrations by microfluidic biochips because of the advantages in saving costly reagents and rare samples. The current state-of-the-art of concentration generation for microfluidic biochips is to construct a database by random design methods. However, due to the complex multidimentional parameters such as molecule diameters, inlets, outlets, etc, the whole process is error prone and time consuming. To speedup database construction and reduce the errors in concentration generation, this paper proposes the first transfer learning-based method based on an artificial neural network model (ANN). Given an initial ANN model, transfer learning method can fine-tune weights of ANN to obtain all ANN models needed in the database, which can significantly reduce the amount of required training data. Computational simulation results show that the time for database construction is reduced from several months to 2 days, and the query error is reduced by 83% compared with the existing method.
Weiqing Ji, Tsung-Yi Ho, Hailong Yao 0002
DAC1
2020 Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network
abstract
According to the complexity of human physiology and variability among individuals, e.g., genes, environment, lifestyle exposures, etc., personalized medicine aims to synthesize the specific efficacious drug for each individual patient. For synthesizing personalized medicine, customized solutions with specific concentrations are required. Equipped with the advantages in saving costly reagents and rare samples, microfluidic biochips are promising in generating different concentrations for personalized medicine. On the one hand, digital microfluidic biochips require the programming control for driving the movement of the droplets, which suffer from random errors caused by imbalanced droplet splitting. On the other hand, existing flow-based microfluidic biochips can only generate linear concentration gradients, which cause significant waste for synthesizing personalized medicine. To address the above issues, this article proposes the first artificial neural network (ANN)-based design method for flow-based microfluidic biochips, which accurately generates the customized concentration gradients. According to the required concentration, an initial chip is first selected from the prebuilt database and then fine-tuned by ANN to better match the required concentration. The computational simulation results show that the induced deviations in generated concentrations are generally less than 0.014, which validates the accuracy of the proposed neural network model.
Weiqing Ji, Tsung-Yi Ho, Hailong Yao 0002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2020 Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips
abstract
Paper-based digital microfluidic biochips (P-DMFBs) have recently emerged as a promising low-cost and fast-responsive platform for biochemical assays. In P-DMFBs, electrodes and control lines are printed on a piece of photograph paper using an inkjet printer and carbon nanotubes (CNTs) conductive ink. Compared with traditional digital microfluidic biochips (DMFBs), P-DMFBs enjoy significant advantages, such as faster in-place fabrication with printer and ink, lower costs, and better disposability. Since electrodes and CNT control lines are printed on the same side of this paper, a critical design challenge for P-DMFB is to prevent control interference between moving droplets and the voltages on CNT control lines. Control interference may result in unexpected droplet movements and thus incorrect assay outputs. To address this design challenge, a control-fluidic codesign methodology is proposed in this paper, along with two demonstrative design flows integrating both fluidic design and control design, i.e., the droplet-oriented codesign flow and the electrode-oriented codesign flow. The droplet-oriented flow is suitable for designing biochips with sparse electrodes and relatively larger number of droplets, whereas the electrode-oriented flow is suitable for biochips with dense electrodes and smaller number of droplets. The computational simulation results of real-life bioassays demonstrate the effectiveness of the proposed codesign flows.
Qin Wang 0005, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li 0001, Haena Cheong, Oh-Sun Kwon, Hailong Yao 0002, Tsung-Yi Ho, Kwanwoo Shin, Bing Li 0005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
2020 URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips
abstract
In high-throughput drug screening applications, as manual drug sample delivery is time-consuming and error-prone, there is an urgent need for accurate and efficient drug sample delivery biochip for large-scale microwell arrays. This paper proposes a new microfluidic biochip architecture, where drugs are automatically prepared with different concentration values, and then delivered into multiple microwells. For large-scale drug sample delivery biochips, the routing of drug sample delivery channels is a very challenging task without effective routing solutions. This paper proposes an ultrafast rule-based escape routing method, called URBER, to address the large-scale routing of drug sample delivery channels, which scales well in both runtime and memory even for a very large problem size. URBER runs very fast because it routes channels based on a set of predefined rules, which avoids runtime consumed in solution space exploration. All benchmarks for 30 ≤ N, M ≤ 100 have been tested, where N and M are the number of columns and rows of the terminal array. Among these benchmarks, about ~91.9% are routed with optimal solutions, and the runtime is order of magnitudes faster than optimal min-cost flow-based methods (speedup is from ~600 to ~340 k). Specifically, for all benchmarks with (M/N) E ((3/4), (4/3)), optimal routing solutions are always obtained. URBER also shows promise of routing large-scale designs with up to 500 k terminals efficiently.
Jiayi Weng, Tsung-Yi Ho, Weiqing Ji, Mengdi Bao, Hailong Yao 0002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3