On-chip power planning is a crucial step in chip design. As process nodes advance and the need to supply lower operating voltages without loss becomes vital, the optimal design of the Power Delivery Network (PDN) has become pivotal in VLSI to mitigate IR-drop effectively. To address IR-drop issues in the latest nodes, a back-side power delivery network (BSPDN) has been proposed as an alternative to the conventional front-side PDN. However, BSPDN encounters design issues related to the pitch and resistance of through-silicon vias (TSV s). In addition, BSPDN faces optimization challenges due to the trade-off between rail and grid IR-drop, particularly in the effectiveness of uniform grid design patterns. In this study, we introduce a design framework that utilizes reinforcement learning to identify optimized grid width patterns for individual VLSI designs on the silicon back-side, aiming to reduce IR-drop. We have applied our design approach to various benchmarks and validated its improvement. Our results demonstrate a significant improvement in total IR-drop, with a maximum improvement of up to −19.0% in static analysis and up to −18.8% in dynamic analysis, compared to the conventional uniform BSPDN.

The semiconductor foundries are now mass-producing 3nm transistors. In this trend, many studies on 2nm node report the potential of future transistors such as forksheet FET (FSFET) from the device perspective. However, only a few studies report the impact of advanced transistors at the full-chip level. Thus, this study focuses on enlightening the potential of FSFET at the full-chip level in the 2nm process compared to the 3nm node currently in mass production. To do this, we present FS2K, the first public 2nm technology library in FSFET, which provides the following results: 1) The simple scaling with no variation in devices or interconnect achieves only about 10% power reduction and area reduction in 2nm processes for FSFET and Nanoshet FET (NSFET). 2) An optimal performance improvement in a 2nm node requires FSFET to be designed in a 4T standard cell that is 1-track reduced from 3nm. Our 2nm 4T-FSFET design achieves -29.5% area reduction and -31.9% power reduction compared to the existing 3nm process. Thus, we emphasize the importance of optimization not only in the device but also in the cell layout for future processes.

The imminent rise in data consumption and the physical constraints of current advanced CMOS scaling hasten the end of the projection to the binary system. For a breakthrough of these issues, the ternary system, known for its superior efficiency in expressing numbers (closest to$\mathrm {e}\approx ~2.7183$) has garnered considerable attention. Among the ternary studies reported, the anti-ambipolar transistor (AAT) is acquiring attention thanks to its unique negative differential resistance (NDR) and anti-ambipolar characteristics (AAC). Moreover, easy-to-fabricate inkjet-printing based AAT was introduced. Therefore, in this paper, we propose a practical design methodology (‘$\mathbf {T^{3}L:} $The Tri-transistor Ternary Logic’) and a set of novel ternary logic based on inkjet-printed AATs and CMOSs. In detail, 1) We propose balanced ternary full adders (BTFA) and prove that inkjet-printed AATs and CMOSs are highly capable of implementing any kind of ternary logic. 2) We propose two design methodologies for ternary logic design: NDR-based Design Method I and AAC-based Design Method II. 3) We present optimization methodology for inkjet-printed ternary circuit stability and provide circuitry to secure sufficient noise margin. We provide a highly-compact BTFA design that requires only 64 transistors and an ultra-low-power BTFA design that reduces power by 84.7% to 98.8% compared to the previous designs.

In recent decades, the performance of binary computers has escalated through transistor scaling. However, due to the impotent forecasts of transistor scaling, ternary systems are regaining attention. Among many ternary device candidates, a passive device called memristor that is based on resistance switching is considered a good candidate when integrated with MOSFETs. Therefore, in this paper, we design various terna-ry logic based on memristors and MOSFETs from primitive logic to sequential logic and perform a thorough diagnosis for circuit design. We highlight design issues that should be resolved (e.g., signal distortion and high static current) and present practical solutions such as “Strength Design.” Then, we report a proper design methodology of sequential circuits considering the spike phenomena of memristor-based gates. We present 16 novel ternary logic cells and circuitry, including the design of the first balanced ternary full-adder (TFA) and memristor-based ternary pulsed-latch (MTPL). By our TFA, we emphasize that it is possible to design the most practical ternary circuits using memristors and MOSFETs. Our TFA uses 97 transistors and 87 memristors, which is the most reasonable TFA design that has the highest potential to be implemented in the near future. Besides, the proposed MTPL uses 16 transistors and 10 memristors, and it occupies only 72.7% of the silicon area, compared to the master-slave ternary flip-flop.

This paper describes graph-based Wave Function Collapse algorithm for procedural content generation. The goal of this system is to enable a game designer to procedurally create key content elements in the game level through simple association rule input. To do this, we propose a graph-based data structure that can be easily integrated with a navigation mesh data structure in a three-dimensional world. With our system, if the user inputs the minimum association rule, it is possible to effectively perform procedural content generation in the three-dimensional world. The experimental results show that the Wave Function Collapse algorithm, which is a texture synthesis algorithm, can be extended to a non-grid shape with high controllability and scalability.