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Divyani Rao

dblp:224/6610 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 33% Distributed systems · 33% Energy-efficient computing · 33%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › DRAM
DRAM power management
0.312018
Cross-Layer Memory Management to Improve DRAM Energy Efficiency · ACM Trans. Archit. Code Optim. 2018
Energy-efficient computing › power management
memory power management
0.312018
Cross-Layer Memory Management to Improve DRAM Energy Efficiency · ACM Trans. Archit. Code Optim. 2018
Distributed systems › distributed resource management
object placement
0.312018
Cross-Layer Memory Management to Improve DRAM Energy Efficiency · ACM Trans. Archit. Code Optim. 2018
Operating systems › resource management
memory management
0.112018
Cross-Layer Memory Management to Improve DRAM Energy Efficiency · ACM Trans. Archit. Code Optim. 2018

Methods — techniques the papers use, named apart from their topics

sampling-based analysis · 0.7object profiling · 0.7
YearPublicationVenuePosition
2018 Cross-Layer Memory Management to Improve DRAM Energy Efficiency
abstract
Controlling the distribution and usage of memory power is often difficult, because these effects typically depend on activity across multiple layers of the vertical execution stack. To address this challenge, we construct a novel and collaborative framework that employs object placement, cross-layer communication, and page-level management to effectively distribute application objects in the DRAM hardware to achieve desired power/performance goals. This work describes the design and implementation of our framework, which is the first to integrate automatic object profiling and analysis at the application layer with fine-grained management of memory hardware resources in the operating system. We demonstrate the utility of this framework by employing it to control memory power consumption more effectively. First, we design a custom memory-intensive workload to show the potential of this approach to reduce DRAM energy consumption. Next, we develop sampling and profiling-based analyses and modify the code generator in the HotSpot VM to understand object usage patterns and automatically control the placement of hot and cold objects in a partitioned VM heap. This information is communicated to the operating system, which uses it to map the logical application pages to the appropriate DRAM modules according to user-defined provisioning goals. The evaluation shows that our Java VM-based framework achieves our goal of significant DRAM energy savings across a variety of workloads, without any source code modifications or recompilations.
Matthew Benjamin Olson, Joseph T. Teague, Divyani Rao, Michael R. Jantz, Kshitij A. Doshi, Prasad A. Kulkarni
ACM Trans. Archit. Code Optim.3