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Jann Horn

dblp:224/9372 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Hardware security and side channels · 100%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels
microarchitectural attacks
0.722019
Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019
Meltdown: Reading Kernel Memory from User Space · USENIX Security Symposium 2018
Hardware security and side channels › side-channel attack › cache side-channel attacks
cache timing attack
0.412019
Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019
Hardware security and side channels
side-channel attack
0.412019
Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019
Hardware security and side channels › microarchitectural attacks › transient execution attack › speculative execution attack
spectre
0.412019
Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack
0.412019
Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019
Hardware security and side channels › microarchitectural attacks
transient execution attack
0.312018
Meltdown: Reading Kernel Memory from User Space · USENIX Security Symposium 2018
Processor architecture and microarchitecture
speculative execution
0.222019
Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019
Meltdown: Reading Kernel Memory from User Space · USENIX Security Symposium 2018

Methods — techniques the papers use, named apart from their topics

return-oriented programming · 0.8fault attack · 0.8
YearPublicationVenuePosition
2019 Spectre Attacks: Exploiting Speculative Execution
abstract
Modern processors use branch prediction and speculative execution to maximize performance. For example, if the destination of a branch depends on a memory value that is in the process of being read, CPUs will try to guess the destination and attempt to execute ahead. When the memory value finally arrives, the CPU either discards or commits the speculative computation. Speculative logic is unfaithful in how it executes, can access the victim's memory and registers, and can perform operations with measurable side effects. Spectre attacks involve inducing a victim to speculatively perform operations that would not occur during correct program execution and which leak the victim's confidential information via a side channel to the adversary. This paper describes practical attacks that combine methodology from side channel attacks, fault attacks, and return-oriented programming that can read arbitrary memory from the victim's process. More broadly, the paper shows that speculative execution implementations violate the security assumptions underpinning numerous software security mechanisms, including operating system process separation, containerization, just-in-time (JIT) compilation, and countermeasures to cache timing and side-channel attacks. These attacks represent a serious threat to actual systems since vulnerable speculative execution capabilities are found in microprocessors from Intel, AMD, and ARM that are used in billions of devices. While makeshift processor-specific countermeasures are possible in some cases, sound solutions will require fixes to processor designs as well as updates to instruction set architectures (ISAs) to give hardware architects and software developers a common understanding as to what computation state CPU implementations are (and are not) permitted to leak.
Paul C. Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas 0004, Michael Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher 0002, Michael Schwarz 0001, Yuval Yarom
IEEE Symposium on Security and Privacy2
2018 Meltdown: Reading Kernel Memory from User Space
Moritz Lipp, Michael Schwarz 0001, Daniel Gruss, Thomas Prescher 0002, Werner Haas 0004, Anders Fogh, Jann Horn, Stefan Mangard, Paul C. Kocher, Daniel Genkin, Yuval Yarom, Michael Hamburg
USENIX Security Symposium7