Cooperative Awareness (CA) is an integral part of Intelligent Transport Systems (ITSs) standardized by the European Telecommunications Standards Institute (ETSI) and targeted to ensure safe and efficient transportation in the future. Miniature Unmanned Aerial Vehicles (UAVs) have been widely utilized in various applications due to their ever-increasing functionalities. Thus, it is a matter of time until the need to integrate them into ITS and human-centric communication ecosystems arises. To enable the benefits of ITS to miniature UAVs, in this paper, a low-cost, low-power, novel UAV-CA Message (CAM) scheme for indoor and outdoor based on Bluetooth Low Energy (BLE) radio access technology is introduced. Furthermore, a proof-of-concept implementation is developed for this BLE-based UAV-CAM, and its performance is investigated using analytical, experimental, and simulation methods. Notably, both the performance for CA over BLE4 legacy advertising and the extended advertising introduced in BLE5 are reported. Our results demonstrate that BLE is able to produce a power-efficient, scalable solution with sufficient range capabilities while keeping up with the traffic requirements of CAM.

Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in network service deployment, there is a huge demand for scalability and flexibility in modern networking infrastructure, which in return has paved way for the introduction of Software Defined Networking (SDN) in core networks. In this paper, we present an FPGA-based switch which is fully compliant with OpenFlow; the pioneering protocol for southbound interface of SDN. The switch architecture is completely implemented on hardware. The design consists of an OpenFlow Southbound agent which can process OpenFlow packets at a rate of 10Gbps. The architecture contains a primary pipeline which is capable of achieving core network throughputs and an auxiliary pipeline leading to the Openflow agent. Single clock cycle Content Accessible Memory (CAM) architecture supports the overall design to achieve its throughput and latency requirements. The proposed architecture speed scales up to 400Gbps while it consumes only 60% resources on a Xilinx Virtex-7 featuring XC7VX485T FPGA. Switch fabric is capable of connecting to a control plane running upon a host PC via PCIe which provides an opportunity at research level to explore SDN in core networks. Moreover, the architecture is experimented for different scaled versions using line rates of 10G, 25G and 100G. By using FPGA based embedded platforms which support sufficient number of ports and their line rates, this architecture can be deployed in core networks.

Convolutional Neural Networks (CNNs) are widely used in deep learning applications, e.g. visual systems, robotics etc. However, existing software solutions are not efficient. Therefore, many hardware accelerators have been proposed optimizing performance, power and resource utilization of the implementation. Amongst existing solutions, Field Programmable Gate Array (FPGA) based architecture provides better cost-energy-performance trade-offs as well as scalability and minimizing development time. In this paper, we present a model-independent reconfigurable co-processing architecture to accelerate CNNs. Our architecture consists of parallel Multiply and Accumulate (MAC) units with caching techniques and interconnection networks to exploit maximum data parallelism. In contrast to existing solutions, we introduce limited precision 32 bit Q-format fixed point quantization for arithmetic representations and operations. As a result, our architecture achieved significant reduction in resource utilization with competitive accuracy. Furthermore, we developed an assembly-type microinstructions to access the co-processing fabric to manage layer-wise parallelism, thereby making re-use of limited resources. Finally, we have tested our architecture up to 9×9 kernel size on Xilinx Virtex 7 FPGA, achieving a throughput of up to 226.2 GOp/S for 3×3 kernel size.