Gate sizing and buffer insertion are crucial for VLSI physical optimization; however, conventional decoupled approaches often yield suboptimal solutions due to uncoordinated resource allocation. Existing simultaneous methods resort to oversimplified timing models or heuristic assumptions, failing to unify the two tasks mathematically rigorously. We present a differentiable physical optimization framework integrating both techniques with GPU acceleration. Key innovations include timing-aware buffer tree skeleton construction, physics-aware modeling, and discrete-aware optimization algorithms. Experiments demonstrate 23% total negative slack (TNS) improvement and 12% worst negative slack (WNS) improvement with similar power consumption and 30× speedup versus CPU-based optimization flow. This work establishes a new paradigm for co-optimizing interdependent physical design tasks with rigorous modeling and efficient computation.

Existing trajectory planning methods for distributed unmanned systems are limited and constrained by data-empowered information from environments. A deep reinforcement learning-based two-phase trajectory planning method is proposed, including the mission transition phase (MTP) and mission maintenance phase (MMP). During MTP, the mobile node transfers from the current to the target position while avoiding obstacles. Meanwhile, assisted communication among nodes in the mission area exists for MMP. The deep learning model is designed for these two phases, respectively, to realize trajectory planning. The optimal model that improves the planning reward is obtained by using experience pools and sampling. Further, it is capable of dealing with complex and high-dimensional optimization as well as adapting to the dynamic environment, making trajectory planning more accurate and efficient. By consuming similar time steps to the optimal path method and 1/3 time steps of coordinate transition methods, the safety of unmanned system is guaranteed and energy consumption is reduced. Moreover, obvious advantages of the method are illustrated in the deployment of large-scale network scenes and auxiliary communication task is fulfilled with simplified processes, resulting in 2/3 and 1/4 computation complexities of particle swarm optimization and scanning methods.

Accurate and efficient power analysis at early VLSI design stages is critical for effective power optimization. It is a promising yet challenging task to model the circuit power at early design stages, especially during placement with the clock tree and final signal routing unavailable. Additionally, optimization-induced circuit transformations like circuit restructuring and gate sizing can invalidate fine-grained power supervision. Addressing these difficulties, we introduce the first circuit-transformation-aware power prediction model at placement stage with robust generalization capabilities. Our technology includes a dedicated clock tree model and an innovative train-and-calibrate scheme that effectively integrates topological and layout features. Compared to the cutting-edge commercial IC engine Innovus, we have significantly reduced the cross-stage power analysis error between placement and detailed routing.

Gate sizing is critical in VLSI design because it significantly influences final design quality. Traditional design flows typically treat gate sizing as a separate step due to its discreteness nature. However, this approach not only undermines the optimization efforts of earlier stages like placement, but also restricts the exploration space for gate sizing. To address these challenges, we introduce an innovative design flow fusing gate sizing with the earlier global placement stage. Our method employs differentiable timing and leakage power objectives and leverages GPU-accelerated computation to enhance design quality directly and efficiently. Our experimental results demonstrate significant improvements in timing and power metrics, with an average improvement of 77.1% in total negative slack (TNS) and 43.5% in worst negative slack (WNS), and meanwhile achieving a reduction in leakage power consumption by 1% compared with one of the most popular design tools, OpenROAD. Our method can speedup the design process by up to 7×.

Static timing analysis (STA) for large-scale modern circuits requires extensive handling of false paths, multi-cycle paths, and other types of path exceptions. Despite the linear nature of timing propagation, we show that exception-aware STA is NP-hard and thus requires a long runtime to solve using conventional CPU-based methods. To overcome this runtime challenge, we propose a general CPU-GPU heterogeneous algorithm, HeteroExcept, that can handle common types of path exceptions and efficiently generate an accurate path report. Our algorithm targets runtime efficiency at the scale of thousands of exception rules and millions of circuit elements. To further improve the performance, we optimize our GPU implementation by introducing a cost-effective data exchange strategy between CPU and GPU. Experimental results demonstrate up to 6.84× and 12.93× speed-up compared to industrial timers, PrimeTime and OpenSTA.

Multi-agent collaboration is the latest trending method to build conversational recommender systems (CRS), especially with the widespread use of Large Language Models (LLMs) recently. Typically, these systems employ several LLM agents, each serving distinct roles to meet user needs. In an industrial setting, it’s essential for a CRS to exhibit low first token latency (i.e., the time taken from a user’s input until the system outputs its first response token.) and high scalability—for instance, minimizing the number of LLM inferences per user request—to enhance user experience and boost platform profit. For example, JD.com’s baseline CRS features two LLM agents and a search API but suffers from high first token latency and requires two LLM inferences per request (LIPR), hindering its performance. To address these issues, we introduce a Hybrid Multi-Agent Collaborative Recommender System (Hybrid-MACRS). It includes a central agent powered by a fine-tuned proprietary LLM and a search agent combining a related search module with a search engine. This hybrid system notably reduces first token latency by about 70% and cuts the LIPR from 2 to 1. We conducted thorough online A/B testing to confirm this approach’s efficiency.

Advancement in information technology has given a tremendous change in the education system. The traditional classroom education system is slowly getting transferred to the modernized system. In this conversion, the students choose to select the courses to learn in their higher education. The selection will aid the student in learning advanced technologies through theoretical and practical methods. In this research work, a data‐driven educational decision‐making system with the support of a course curriculum is analyzed with student’s response after the course. The educational decision‐making is implemented with the help of the mobile learning technology designed and maintained by the colleges and universities. For performing the analysis, the student response dataset is given as input to the fuzzy logic system to perform the analysis. The research shows that mobile learning technology with the fuzzy logic system has provided better decision‐making analysis to curriculum optimization for the student and teachers.