Internet of Things (IoT) edge nodes are often battery-powered or energy-harvesting and must operate under tight energy and area constraints while still supporting low-latency local decision-making. Since wireless transmission is energy-expensive, IoT increasingly relies on in-situ edge processing, which demands ultra-low-power and compact compute blocks, yet further complementary-metal-oxide-semiconductor (CMOS) scaling is constrained by leakage, interconnect congestion, and rising power density. Atomic silicon quantum-dot (ASQD) technology offers a promising alternative by enabling computation via charge configuration rather than current flow, potentially providing very low energy operation and highly compact layouts; however, large-scale ASQD circuits remain challenging due to coupling-induced stability limitations. To address this, we propose a low-power ASQD-based arithmetic circuit for low-power edge IoT computing that supports four distinct operations under a unified multiplexer (MUX) controlled structure. The design follows an integration-aware methodology in which candidate primitives are benchmarked at the gate level (Atoms/Area/Energy), and optimized variants are selected to minimize cumulative arithmetic logic unit (ALU) level cost. ALU-level scaling shows reductions of approximately 69–79% in occupied area and 43–51% in total energy compared with representative literature libraries, and SiQAD simulations verify stable operation. These results indicate that the proposed circuit can serve as an enabling compute primitive for future ASQD IoT platforms.

Digital Image Processing (DIP) is the ability to manipulate digital photographs via algorithms for pattern detection, segmentation, enhancement, and noise reduction. In addition, the Internet of Things (IoT) acts as the eye and system for all DIP in various applications. It can possess a camera or another image sensor in order to capture real-time data from its environment. All vital data is processed by image processing in such a way that it recognizes the object, detects an anomaly, and automatically decides in real-time. In addition, in an IoT system, the median filter is the technique used for noise reduction by substituting the value of the pixel with the central value of the surrounding pixels. It provides speed and efficiency for quick analysis in all IoT systems. However, the images can get corrupted, especially in resource-constrained IoT devices with small cameras, because of random glitches. Moreover, using new quantum technology like atomic-scale silicon dangling bond (DB) logic circuits, which have advanced in fabrication and become a strong contender for field-coupled nano-computing, can solve previous problems in IoT systems. In this paper, we propose a unique quantum CSM based on two new proposed Mux and De-mux. The proposed CSM can be used for computational circuits like median filter circuits (MFC) in a wide range of digital circuits, specifically IoT devices. The proposed design is verified and validated using the powerful SiQAD tool. When comparing CSM to the newest designs, the suggested quantum circuit uses 85% less energy and takes up 61% less area.

Because of recent technological developments, such as Internet of Things (IoT) devices, power consumption has become a major issue. Atomic silicon quantum dot (ASiQD) is one of the most impressive technologies for developing low-power processing circuits, which are critical for efficient transmission and power management in micro IoT devices. On the other hand, multipliers are essential computational circuits used in a wide range of digital circuits. Therefore, the multiplier design with a low occupied area and low energy consumption is the most critical expected goal in designing any micro IoT circuits. This article introduces a low-power atomic silicon-based multiplier circuit for effective power management in the micro IoT. Based on this design, a$4\times 4$-bit multiplier array with low power consumption and size is presented. The suggested circuit is also designed and validated using the SiQAD simulation tool. The proposed ASiQD-based circuit significantly reduces energy consumption and area consumed in the micro IoT compared to most recent designs.

Reversible logic has recently gained significant interest due to its inherent ability to reduce energy dissipation, which is the primary need for low-power digital circuits. One of the newest areas of relevant study is reversible logic, which has applications in many areas, including nanotechnology, DNA computing, quantum computing, fault tolerance, and low-power complementary metal-oxide-semiconductor (CMOS). An electrical circuit is classified as reversible if it has an equal number of inputs and outputs, and a one-to-one relationship. A reversible circuit is conservative if the EXOR of the inputs and the EXOR of the outputs are equivalent. In addition, quantum-dot cellular automata (QCA) is one of the state-of-the-art approaches that can be used as an alternative to traditional technologies. Hence, we propose an efficient conservative gate with low power demand and high speed in this paper. First, we present a reversible gate called ANG (Ahmadpour Navimipour Gate). Then, two non-resistant QCA ANG and reversible fault-tolerant ANG structures are implemented in QCA technology. The suggested reversible gate is realized through the Miller algorithm. Subsequently, reversible fault-tolerant ANG is implemented by the 2DW clocking scheme. Furthermore, the power consumption of the suggested ANG is assessed under different energy ranges (0.5Ek, 1.0Ek, and 1.5Ek). Simulations of the structures and analysis of their power consumption are performed using QCADesigner 2.0.03 and QCAPro software. The proposed gate shows great improvements compared to recent designs.

Summary Quantum‐dot cellular automata (QCA) is a very interesting nanoscale technology. Ultradense structure and ultralow power consumption are the most important features of QCA compared to CMOS. QCA circuits often suffer from various types of manufacturing defects and are therefore prone to fault. Hence, the design of fault‐tolerant circuits in QCA technology is considered a necessity. In this paper, a novel fault‐tolerant three‐input majority gate is presented using 12 simple and rotated cells in QCA technology. The proposed structure is investigated against all kinds of cell omission, extra‐cell deposition, and cell displacement defects. The simulation results are verified by QCADesigner 2.0.3, and it showed 100%, 89.29%, and 100% tolerance against single‐cell omission, double‐cell omission, and extra‐cell deposition, respectively. In addition, the proposed structure is robust against cell displacement defects. Finally, using the proposed structure, a novel coplanar full adder is presented. The results were compared and indicated that the proposed designs are more reliable than the existing designs. Furthermore, QCAPro power estimator tool was employed to estimate the energy dissipation of the proposed structure.