Considering the potential benefits to lifespan and performance, zoned flash storage is expected to be incorporated into the next generation of consumer devices. However, due to the limited volatile cache and heterogeneous flash cells of consumer-grade flash storage, adopting a zone abstraction requires additional internal hardware design to maximize its benefits. To understand and efficiently improve the hardware design on consumer-grade zoned flash storage, we present ConZone—the first emulator tailored to the characteristics of consumer-grade zoned flash storage. Users can explore the internal architecture and management strategies of consumer-grade zoned flash storage and integrate the optimization with software. We validate the accuracy of ConZone by realizing a hardware architecture for consumer-grade zoned flash storage and comparing it with the state-of-the-art. We also make a case study for read performance research with ConZone to explore the design of mapping mechanisms and cache management strategies.

F2FS improves performance and longevity through out-place updates, and is now wildly used in the real world. However, additional overhead is introduced to support such design, which leads to a significant performance bottleneck when performing fsync(). Through a series of experimental observations, the paper reveals the impact of dnode page writeback on throughput and fsync() latency. The serial flushing of data pages and dnode pages in the current fsync() design limits the potential for parallel write back and fails to fully utilize the parallelism of flash devices. We then deeply look into the current fsync() design and find the main difficulty of paralleling fsync() is the dependency between dnode pages and data pages. Based on these findings, we propose a new dual-thread design that significantly reduces the total latency of fsync() and improves throughput by pre-allocating data pages. Then, we give two optimizations to reduce overhead. A red-black tree is introduced to cache old block addresses for better node management performance. A linked list is introduced to avoid contention of the page cache for better page performance. We implemented our method in Linux Kernel, and the experimental results show that our dual-thread design can decrease fsync() latency and increase write throughput in different situations.