Transistor-level design is pivotal for the accurate evaluation of FPGA architectures. Since traditional linear models are increasingly inadequate in advanced technology nodes, simulation-driven approaches have become the standard for FPGA architecture exploration. However, due to the non-analytical nature of delay measurements from simulations, the transistor sizing process becomes a black-box optimization problem. COFFE2 [1], [2], the state-of-the-art academic sizing tool employs a division-based brute-force approach, which is relatively time-consuming and may lose optimal solutions. In this paper, we propose a two-phase transistor sizing methodology and enhance the COFFE2 framework with Bayesian Optimization, which is well-suited for black-box optimization problems. Our proposed approach not only achieves a 11.7% improvement in the quality of results but also reduces runtime by ~40%-70%. Through extensive benchmarking on a complete design flow, from transistor-level sizing to routing with VTR benchmarks, we demonstrate that FPGA architectures optimized by our approach offer an 11.0% reduction in the area-delay product, proving the efficacy of our method.

Look-up table (LUT)-based programmable logic blocks (PLBs) serve as the foundation for FPGAs. As increasing the input number of LUTs to improve logic capacity will introduce exponential area overhead, substantial research has focused on designing more efficient alternatives. Previous approaches primarily design dedicated hardware by analyzing the distribution of Boolean functions and implementing those with high frequency. However, these approaches face scalability challenges due to the explosive growth in the function space. In this paper, we consider the topology of cuts rather than Boolean functions they represent. By identifying topologies that occur commonly in cuts and integrating them with LUTs, we propose a new 8-input PLB architecture, named FLAIC. This architecture incurs only a slight area overhead compared to a 6-LUT while achieving logic capacity comparable to that of an 8LUT. Post-synthesis results demonstrate that FLAIC reduces the logic levels by over 20 % and the number of PLBs by more than$\mathbf{1 0 \%}$, compared to 6-LUTs. Additionally, post-implementation results show improvement in critical path delay by 10.6 % and a reduction in the number of Configurable Logic Blocks (CLBs) by 5.3 % on MCNC and VTR benchmarks, compared to the Intel Stratix 10-like architecture.

The routing architecture significantly impacts the performance of modern FPGAs, motivating extensive research into its design space exploration (DSE). However, DSE efficiency is hindered by non-generalizable parametrization methods and considerable runtime overhead of FPGA architecture evaluation tools. In this paper, we propose GEF, a GNN-based FPGA Evaluation Framework that predicts routability and area-delay product (ADP) across various routing architectures. In GEF, we introduce Intra-Tile Graph, a novel intermediate representation (IR) that encodes global routing patterns in a compact form, serving as the input to predictors. The Routability Predictor (Rou-P) integrates Self-Attention Pooling (SAGPool), while the ADP Predictor (ADP-P) benefits from intermediate supervision through auxiliary node-level labels. Experimental results demonstrate the high accuracy of GEF, with Rou-P achieving 94.56% and ADP-P 94.57 %, respectively. We also conduct ablation studies, which further validate that GEF achieves substantial enhancements through efficient architecture modeling and timingaware analysis. Finally, a case study on routing architecture exploration with the incorporation of GEF is presented, which achieves a$\mathbf{1 5} \boldsymbol{\times}$speedup and enhanced improvements. Our codes are are available from https://github.com/RapidFlex/GEF.

On one hand, aiming at the prominent problem of improving the reliability of Faster-than-Nyquist (FTN) wireless transmission, abandoning the channel estimation, we propose the Radial Basis Function Least Squares Support Vector Machine (RBF LSSVM) algorithm based on Intelligent Signal Processing for FTN equalization and form FTN time domain transverse filter equalizer. The model of FTN wireless communication system based on equalization of LSSVM algorithm is established by adding 50-bit training sample sequence module. On the other hand, in the FTN transmission BPSK modulation system receiving terminal, we propose joint research equalization of LSSVM algorithm and adaptive channel decoding scheme of Chase algorithm, to improve the reliable transmission performance of FTN wireless communication. The threshold value is 20, and the adaptive 2-D Turbo Product Codes (TPC) encoding and decoding is simulated by four iterations. The BER performance of FTN wireless communication combined with LSSVM algorithm and TPC adaptive decoding is simulated.

Learning to estimate depth and ego-motion from video sequences via deep convolutional networks is attracting significant attention for potentially wide computer vision applications. Most prior work in unsupervised depth learning use monocular video sequences as the input of their networks. However, their results need a scale factor that is computed frame-to-frame to maintain a stable relative scale. In this paper, we propose an unsupervised learning framework for the task of joint depth and ego-motion estimation from stereo sequences. The usage of stereo sequences can provide both spatial (left to right) and temporal (forward to back-ward) photometric warping constrains for supervised learning and allow for an absolute scale factor for the scene depth and camera pose, which is of great significance for vision guidance. Experiments on the KITTI driving dataset reveal that our framework outperforms state-of-the-art results employing unsupervised neural networks.

The structured and redundant imagery of light field cameras can provide more robust depth estimation results while on the other hand demands a huge computation power, which limits its real-time applications, such as online industrial monitoring, 3D endoscopic surgery etc. This paper extends the classical SGM(Semi-global matching) [1] algorithm to light filed multi-view stereo framework, which can acquire sub-pixel level disparity estimation to cope with the micro-baseline of light field cameras. The whole algorithm is tailored for parallelization on GPU exploiting multi-stream asynchronization, multi-thread allocation, and multi-type memory management. The results show that our method’s execution time is less than 50ms on NVIDIA 1080Ti, which to our knowledge is the fastest among reported geometry based methods while keeping a comparative accuracy performance.