Advancement in power electronic converters (PEC) are driven by the need for controllable, flexible, and compatible grid connected devices. In the medium voltage (MV) realm, modular multilevel converters (MMC) have become a favorite in the power systems industry for their suite of benefits. MMCs have been shown to operate as excellent high voltage conversion equipments and active front ends (AFE) in ac application. Furthermore, back-to-back (B2B) MMC configurations have been explored for use as IEEE 1547-2018 compliant direct-connected grid inverter. This paper demonstrates application of an advanced hardware-in-the-loop (HIL) testbed to test a MV PEC. The proposed HIL testbed unifies controller hardware-in-the-loop (CHIL) and power hardware-in-the-loop (PHIL) capabilities and enables MV MW-scaled development process for grid application. A third generation 10 kV silicon-carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET)-based MMC with a middle switching cell was developed using the process laid out in the paper, and experimental results from the HIL testbed operating at 250 kVA, 7 kVdc, 3.64 kV line-to-line rms 60 Hz are exhibited. Additionally, the developed MMC demonstrates robust response to IEEE 1547-2018 scenarios. From the results, the development methodology and the MMC are validated, providing excellent testing capability for future grid-connected devices.

Modular multilevel converter (MMC) is a highly suitable converter for medium- and high-voltage applications. Its structure is based on the series connection of many submodules (SMs). While the introduction of 10 kV SiC MOSFET modules has enabled higher voltage and switching frequencies for each SM using simple configurations, this also exacerbates operational challenges, including electrical stresses. Consequently, the design and evaluation of SMs under these conditions are crucial for ensuring reliable operation. This paper focuses on the electrical design and evaluation for a 10 kV SiC power module-based SM in a medium-voltage MMC with middle SMs. First, stray inductance of the PCB busbar with different connections are evaluated, providing guidance to select proper configuration with smaller stray inductance. Then, surface electric field intensity on the customized PCB busbar under various voltage stresses are evaluated to prevent partial discharge as much as possible. Finally, to evaluate the electric field distribution in the SM, electric fields of the entire core area of a SM, including the power module, gate drivers, PCB busbar, heatsink, and copper bars, are analyzed under full dc voltage and realistic switching stress with high dv/dt. The stray inductance and partial discharge characteristics of the PCB busbar are verified experimentally, which align with the design and evaluation results very well. The functionalities of all the individual SMs are experimentally verified by 55-min continuous operation under full voltage and rated output current. The functions of the SM were further confirmed in full-power tests of a downscaled 250 kVA MMC.

With the emergence of diverse services and the development of native artificial intelligence (AI), 6G network is expected to satisfy higher performance requirement by supporting deep convergence of computing and communication. As an important development trend, AI-embedded base station (BS) with computing resources should be considered. However, in some busy-traffic cells, it is difficult for a single BS to serve all users due to its limited computing resources. In this paper, a novel collaborative-computing based system model is proposed for computing-constrained BSs, in which the shared computing resources are introduced to finish both communication protocol and application processing. In addition, a new user association (UA) scheme based on a hierarchical double auction model is designed to improve the long-term network capacity. Simulation results demonstrate that, compared with several typical UA algorithms, the proposed scheme could increase the served user number and throughput significantly without energy efficiency degradation, which is proved a promising approach for wireless networks with integrated computing and communication.

Although medium voltage dc (MVdc) power system is promising to provide flexible, robust, and highly power dense power distribution systems for various applications, the dc power systems suffer from short-circuit fault management issues. To solve the issue, a hybrid dc circuit breaker with piezoelectric actuated fast mechanical switch (FMS) and sequential metal oxide varistors insertion scheme has been developed. In the hybrid dc circuit breaker, to commutate fault current from the FMS to solid-state switches and then, keep zero current through the FMS, a gate voltage-based fault current commutation strategy was developed. The method regulates the current through FMS by adjusting the gate voltage of IGBTs and, thus, the voltage across the solid-state branch without switching of the IGBTs. The paper formulates a model of the de circuit breaker based on the gate voltage-based fault current commutation strategy. From the model, a sufficient condition for enabling the zero-current opening capability is identified, consequently determining the adjustment range of gate voltage-based method, i.e., the limits of voltage across the series of IGBTs. In addition, an analytical solution of the current through FMS is obtained and design guidelines for the gate voltage controller parameters are provided. The analytical solution matches SPICE simulation with detailed IGBT model very well, which verifies the effectiveness of gate voltage-based fault current commutation.

Increasing penetration rate of the renewable energy resources in conjunction with emergence of new dynamic loads such as electric vehicles, necessitate more flexible, efficient, and economical operation of the power grid. To maximize utilization of the power system infrastructure in an efficient and economical way, partially-rated solid-state transformer (PSST) has been proposed to control the power flow. In this paper, new PSSTs based on the AC-AC modular multilevel converter (MMC) are proposed. The proposed PSSTs borrow the salient features of the MMC and are capable of controlling power flow of the grid. Simulation studies in the PSCAD/EMTDC software environment are carried out to validate the performance and effectiveness of the proposed MMC-based PSSTs and the supporting control methods.

The modular multilevel converter (MMC) has become the most attractive converter topology for medium/high-power applications. However, uneven power loss distribution and thermal loading among the semiconductor devices of each submodule (SM) compromise the reliability and lifetime of the converter. In this paper, an active thermal loading control method for the MMC is proposed to simultaneously (i) minimize the total semiconductor power loss and (ii) balance the thermal loading of the semiconductor devices within each submodule. In the proposed method, a multi-objective optimization problem is formulated and solved to establish a trade-off between the total power loss and the power loss of the semiconductor devices with the highest thermal loading. Subsequently, the Pareto optimal solutions for circulating currents, output common-mode voltage, and capacitor voltages are explored. Performance and effectiveness of the proposed method are verified by simulation and experimental studies.