This paper revisits the Miller theorem in linear periodically time-varying networks. Using this, we provide an intuitive technique to analyze Miller N-path filters. Earlier works either considered the amplifier to be a voltage-controlled voltage source (VCVS) instead of a voltage-controlled current source (VCCS) or analyzed the Miller N-path filters from scratch. As an alternative, we show how the analysis can be greatly simplified even in the presence of a VCCS by using the Miller theorem appropriately. Using this, we reduce the Miller N-path filter as a cascade of two regular N-path filters. Unlike the equivalent circuit shown in earlier works, this is an exact model and has no approximations. Hence, by re-using the extensive analysis already done for regular N-path filters, the Miller N-path filter is readily analyzed. The model obtained also helps us make the following observations in a more intuitive manner: i) the overall bandwidth depends on the transconductance, ii) the out-of-band gain can be optimized by choosing the switch resistance to be 1/Gm. Simulation results validating the model and the observations are also presented.

This paper proposes a technique to reduce the steady-state error and increase the settling speed of closed-loop switched-capacitor (SC) amplifiers using floating-inverter amplifiers. The proposed idea takes inspiration from flip-around sample-and-hold and capacitor stacking to realize the amplification with fast settling, while the steady-state error is reduced in a way similar to correlated-level-shifting (CLS). However, unlike CLS, which requires three phases, the proposed flip-around level-shifting requires only two clock phases and hence is highly efficient when used with dynamic amplifiers, like the floating inverter amplifier (FIA). We show that this technique has a much faster closed-loop settling than conventional SC amplifiers, resulting in significant power savings in the FIA. Simulation results of an SC amplifier designed in a 180nm process, with the proposed technique and that of a conventional SC amplifier with CLS, are shown to validate the claims.

This paper explains how the Miller theorem can be applied to analyze a two-stage Miller-compensated opamp and get some insights regarding the pole-zero positions. It is known that one should use the frequency-dependent gain when applying the Miller theorem to get the exact results. But, what is sometimes overlooked is that applying the theorem is non-trivial when dealing with a voltage-controlled current source (VCCS). This is because the voltage gain of the VCCS also depends on the feedback impedance. Instead of computing this voltage gain, we do a source transformation, making it amenable for a straightforward application of the Miller theorem in a two-stage Miller opamp. We also derive an equivalent RC model for the impedance at the input and output and give a qualitative explanation for the same. This gives a different perspective to understand the pole-zero positions, and also brings out the “hidden state” (unobservable/uncontrollable state, as known in control theory) present in a two-stage Miller opamp. Simulation results confirm the accuracy of the derived equivalent RC model.

A new method is presented for converting any continuously running discrete-time delta-sigma modulator (DTDSM) into a multi-channel ADC by adding only a digital filter at the output. The inputs are multiplexed and fed to the ADC directly. The crosstalk that would exist if the decimation filter output is demultiplexed directly is canceled using the proposed modulated-sinc-sum digital filter. Compared to resetting the DSM and converting it to an incremental DSM, the proposed technique is at least$1.57\times $more power-efficient. A prototype two-channel ADC clocked at 6.144 MHz with a channel bandwidth of 22 kHz demonstrates the proposed technique. Fabricated in a 180 nm CMOS process, the prototype chip consumes 1 mW/channel, including the digital filters, and achieves a peak SNR/DR of 94.4 dB/98.5 dB. The inter-channel crosstalk is restricted to less than −93 dBc across the entire bandwidth and across temperature.

This paper presents a switched-capacitor integrator for discrete-time delta-sigma modulators. Compared to the conventional implementations, the proposed switched-capacitor integrator reduces the power consumed by the input buffer that drives the delta-sigma modulator, by a factor of two. The proposed integrator samples the input in two non-overlapping phases instead of sampling it in a single phase. This way, the input capacitance can be equally distributed among the two phases, resulting in a 2× reduction in the switched capacitor load that needs to be driven by the input buffer. We further show that doing this also introduces notches in the signal-transfer- function of the modulator at odd-multiples of the sampling frequency, thereby preventing aliasing from those frequencies. The proposed integrator is used to design a fourth-order DTDSM in a 180 nm CMOS process. Simulation results show that the modulator achieves a peak signal-to-noise ratio (SNR) of 97.9 dB while consuming 0.86 mW of power.