An explainable AI framework for flood detection in SAR images is proposed. Compact encoder-decoder CNNs are used within the framework to achieve flood segmentation, with their output results fed to a Grad-CAM explainer so as to introduce trustworthiness to a stakeholder from naive thresholding selection during post-processing steps. The proposed framework is evaluated on the ETCi 2021 dataset using three different CNNs, resulting in more than 97% accuracy, while descriptive statistics on the Jaccard score are used to indicate the CNNs improper generalization towards the dataset. Edge cases highlight the importance of using Grad-CAM in complement with the CNN when the latter struggles to segment small regions due to thresholding.

This work proposes an interpretable Deep Learning framework utilizing Vision Transformers (ViT) for the classification of remote sensing images into land use and land cover (LULC) classes. It uses the Shapley Additive Explanations (SHAP) values to achieve two-stage explanations: 1) bandwise feature importance per class, showing which band assists the prediction of each class and 2) spatial-wise feature understanding, explaining which embedded patches per band affected the network's performance. Experimental results on the EuroSAT dataset demonstrate the ViT's accurate classification with an overall accuracy 96.86 %, offering improved results when compared to popular CNN models. Heatmaps in each one of the dataset's existing classes highlight the effectiveness of the proposed framework in the band explanation and the feature importance.

The so far dominant Von Neumann architecture is being challenged by the energy demanding communication bottle-neck between processing and memory units. To address this issue, in-memory computing is employed for their co-location, with memristive crossbar arrays playing an important role towards this goal. Motivated by the above, this work introduces a timing-based programming of a memristor crossbar array for sequence generation in Stochastic Computing (SC). Its operation principle is based on the stochastic nature of the memristor devices forming the crossbar array, where their programming is regulated by the switching probability that follows the Poisson distribution, controlled by pulse amplitude and duration. The timing-based programming of the proposed crossbar array increases the discretization levels of the output probability values, thereby offering more accurate control when compared to programming schemes that consider only the pulse amplitude. The memristor's stochasticity along with the crossbar's inherent parallelism opens the in-memory design space allowing SC elements to be used as sequences are generated efficiently. Simulation results on different programming pulse-width precisions highlight the proposed crossbar's effectiveness in sequence generation, supported by mean absolute error (MAE) results in a standard SC arithmetic operation. Process variations stemming from the crossbar array affecting the sequence generation in SC are investigated.

An interpretable deep learning framework for land use and land cover classification (LULC) in remote sensing using SHAP is introduced. It utilizes a compact CNN model for the classification of satellite images and then feeds the results to a SHAP deep explainer so as to strengthen the classification results. The proposed framework is applied to Sentinel-2 satellite images containing 27000 images of pixel size 64 × 64 and operates on three-band combinations, reducing the model’s input data by 77% considering that 13 channels are available, while at the same time investigating on how different spectrum bands affect predictions on the dataset’s classes. Experimental results on the EuroSAT dataset demonstrate the CNN’s accurate classification with an overall accuracy of 94.72%, whereas the classification accuracy on three-band combinations on each of the dataset’s classes highlights its improvement when compared to standard approaches with larger number of trainable parameters. The SHAP explainable results of the proposed framework shield the network’s predictions by showing correlation values that are relevant to the predicted class, thereby improving the classifications occurring in urban and rural areas with different land uses in the same scene.

A general methodology to derive analytically the statistical properties of stochastic computing finite-state machines (SFSMs) is introduced. The SFSMs, expressed as Moore ones, are modeled using Markov Chains (MCs), enabling the derivation in closed form of their output sequences’ statistical properties, including their expected value, their auto- and cross-correlation, their auto- and cross-covariance, their variance and standard deviation as well as their mean squared error. An MC overflow/underflow probability model accompanies the methodology, allowing to calculate analytically the expected number of steps before overflows/underflows, setting the guidelines to select the register’s size that reduces erroneous bits originating from them. In the proposed methodology both the input sequence length and the number of the SFSMs’ states are considered as parameters, accelerating the overall design procedure as the necessity for multiple time-consuming numerical simulations is eliminated. The proposed methodology’s accurate modeling capabilities are demonstrated with its application in two SFSMs selected from the stochastic computing literature, while comparisons with the numerical experiments justify its correctness.

This work presents adder and subtracter architectures for stochastic computing (SC). In contrast to standard approaches, the result of their operation is nonscaling, i.e., X ± Y, and this is achieved via a deterministic operation based on a counting process. These properties result in an improved tradeoff between accuracy and stochastic sequence length, fast convergence, and the potential for cascaded, scale-dependent (e.g., nonlinear) stochastic computations providing with flexibility on the design level. The architectures are modeled using Markov chains (MCs) allowing for detailed understanding of their proper operation supported with analytical derivations. Using modified MC models, the adder and subtracter's internal register size is analytically calculated providing guidelines for its optimal size selection based on accuracy requirements and stochastic input sequences lengths. Both architectures are simulated in MATLAB and are designed in Synopsys to compare their performance to that of existing ones in terms of computational accuracy and hardware resources. Finally, to demonstrate the adder's efficacy, we use it as a building block to realize a 3×3 convolution kernel and then perform a standard digital image processing task. The results are compared to those achieved using adder architectures from the SC literature.

Max & min architectures for stochastic computing (SC) are introduced. Their key characteristic is the utilization of an accumulator to store the signed difference between the two inputs, without randomizing sources. This property results in fast-converging and highly accurate computations using short sequence lengths, improving on the latency–accuracy tradeoff of existing SC max–min architectures. The operation of the proposed architectures is modeled using Markov Chains, resulting in in-depth analysis, the derivation of their statistical properties, and guidelines for selecting the register’s size to achieve overall design optimization. The computational accuracy and the hardware requirements of the proposed architectures are compared to those of existing ones in the SC literature, using MATLAB and Synopsys Tools. The efficacy of the proposed architectures is demonstrated by realizing a$3 \times 3$median filter and using it in an image processing application.

Stochastic computing has been successfully applied in a plethora of applications, including machine learning, computer vision and soft coding/decoding, due to its low complexity, chip area, and power consumption advantages, as well as its tolerance to soft errors. Among the four fundamental numerical operations, addition, subtraction and multiplication are simple to realize stochastically. Division however is significantly more challenging and complex. This work introduces a new architecture for stochastic division in unipolar format using a deterministic finite state machine. In contrast to the existing architectures, the proposed divider does not require any internal stochastic number generator, which makes it more versatile, compact and easy to implement. The divider's accuracy is defined based on mean absolute error metrics and it is estimated using MATLAB simulation. Applications of the proposed divider in image processing are presented demonstrating its accuracy and efficiency in realistic systems.

Internet of Things growth requires the development of low power and low cost wireless transceivers. Here, we present three recently developed all-digital frequency synthesizer architectures which can be used as transmitters for Internet of Things applications. These all-digital transmitters are based on different sigma-delta modulator architectures, varying in performance and hardware complexity. The operation principles of the three proposed architectures are described. Then, proof-of-concept FPGA implementations of these architectures are presented and compared in terms of hardware resources and speed. Their performance is tested using 32-QAM modulated signals. Finally, conclusions are drawn to help the reader select the most suitable architecture for a given application.

A hardware architecture for the implementation of Multi-Step Look-Ahead Sigma-Delta Modulators (MSLA SDMs) is presented. MSLA SDMs offer superior performance than conventional single-bit SDMs for a multitude of applications relying on single-bit signal representation. However, traditional look-ahead SDMs have very high algorithmic complexity and their hardware implementation does not allow for real-time operation. MSLA SDMs overcome this problem by transforming the minimization problem associated with traditional look-ahead SDMs. A proof-of-concept FPGA implementation of a specific MSLA SDM is discussed and compared to a conventional single-bit SDM in terms of performance and hardware complexity. It is demonstrated that MSLA SDMs are a viable alternative to conventional single-bit SDMs when better performance with moderate additional hardware complexity are required.