The evaluation of logic locking methods has long been predicated on an implicit assumption that only the correct key can unveil the true functionality of a protected circuit. Consequently, a locking technique is deemed secure if it resists a good array of attacks aimed at finding this correct key. This paper challenges this one-key premise by introducing a more efficient attack methodology, focused not on identifying that one correct key, but on finding multiple, potentially incorrect keys that can collectively produce correct functionality from the protected circuit. The tasks of finding these keys can be parallelized, which is well suited for multi-core computing environments. Empirical results show our attack achieves a runtime reduction of up to 99.6% compared to the conventional attack that tries to find a single correct key.

The ever-increasing propensity for intellectual property (IP) reuse has reduced the design productivity gap in the supply chain. As a consequence, protecting IPs has become more difficult since IP vendors now make their IPs more flexible so that they can be reused in other designs for greater profits. This has made IP piracy and infringement easier than ever. IP watermarking can detect IP piracy and infringement and it has been an active research topic for the past decade. Various watermarking techniques have been discussed in the literature that embed circuitry into IP to provide proof of ownership. But, in most RT-level watermarking methods, the watermarking circuit is separate from IP functionality and can be easily identified and tampered with. In this paper, we propose CAPEC, a Cellular Automata (CA) guided watermarking technique that embeds watermarking circuits into the don’t care states of the FSM. The watermarking function is a set of configurable CA rules tightly coupled with the functional states of the FSM. CAPEC generates a signature in a challenge-response-based protocol, is resistant to identification, tampering, and removal attacks, and has minimal overhead. We also analyze and evaluate the efficiency of the technique and its resilience to different attacks for varying challenge size and CA rules. After watermarking different benchmarks, the watermark overhead was found to be negligible and formal verification proved no changes to the functional circuit.

The pursuit of manufacturing cost reduction reshaped the conventional system-on-chip (SoC) design and manufacturing flow into the horizontal business model. In this model, the design house loses control of the design during the manufacturing process. Therefore, this shift has introduced potential vulnerabilities at each stage of the flow and provides adversaries ample opportunities to cause piracy, security, and trust concerns. Further, SoCs deployed in IoT, smart, and mission-critical devices contain sensitive assets to perform security-critical applications, requiring an on-chip security engine (SE) to ensure protecting assets and secure operation throughout the lifecycle. In this paper, we present an end-to-end secure SoC lifecycle management flow that establishes trust at each stage of the manufacturing process, prevents potential security threats, provides secure provisioning schemes, and protects the chip from in-field and supply chain vulnerabilities.