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Liewei Xu

dblp:227/9367 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2022
0000-0002-8422-3409ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 62% Hardware accelerators and domain-specific architectures · 27% Reconfigurable computing and FPGAs · 10%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › soft errors
single-event upset
0.612022
SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs · Sci. China Inf. Sci. 2022
Hardware reliability and fault tolerance
soft errors
0.612022
SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs · Sci. China Inf. Sci. 2022
Hardware reliability and fault tolerance › redundancy › modular redundancy
triple modular redundancy
0.612022
SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs · Sci. China Inf. Sci. 2022
Machine learning › Efficient and distributed learning
model compression
0.412019
Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions · FPGA 2019
Machine learning › Efficient and distributed learning › model compression
pruning
0.412019
Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions · FPGA 2019
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.412019
Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions · FPGA 2019
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
sparse neural network acceleration
0.412019
Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions · FPGA 2019
Reconfigurable computing and FPGAs › FPGA accelerator
FPGA accelerator architecture
0.112019
Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions · FPGA 2019

Methods — techniques the papers use, named apart from their topics

structured pruning · 0.8dual channel data scheduling · 0.8data selection multiplexer design · 0.8
YearPublicationVenuePosition
2022 SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs
Bingxu Ning, Lingyun Ke, Gengsheng Chen, Ze He, Liewei Xu, Jie Liu 0032
Sci. China Inf. Sci.9
2019 Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions
abstract
In this study, we propose a software-hardware combined solution for efficient sparse neural network computing. Much of the connections between each layers are pruned in sparse neural network. Usually the weights are in compressed format, but the corresponding feature map data need to be pared before passing to computation engine. Since the compressed weights require indirect memory access, there needs a large amount of multiplexers to locate the data position. Motivated by this, we propose a new architecture with a much smaller data selection multiplexer design. In our hardware architecture, the data are selected in a smaller range so that the scale of multiplexer can be reduced. This is paired with our software network pruning method. Compared with the structured or pattern-based pruning method, our algorithm does not impose such restriction and just ensure that there are same numbers of non-zero elements in each z-channel array of the weights. The non-zero elements can be distributed at any position in the array. We also use dual channel for better efficiency on data scheduling. Our experimental results show that our architecture can reach 3x overall speedup for 25% sparsity networks when compared with non-sparse engines with the same amount of computing resources. In the future, we plan to further improve our pruning algorithm, and tape out our hardware design.
Yanjie Gu, Tieli Sun, Zhenhao Feng, Liewei Xu
FPGA6