EDBT 2026 Demo / reviewers in the wild / expert
Seaghan Sefton
dblp:228/2689
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2018
0000-0001-8272-1183ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Systems and software security · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 50% Energy-efficient computing · 50% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Systems and software security
information flow control |
0.3 | 1 | 2018 | GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Systems and software security › program analysis
runtime monitoring |
0.3 | 1 | 2018 | GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Energy-efficient computing
power management |
0.1 | 1 | 2018 | GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Methods — techniques the papers use, named apart from their topics
verilog generation · 0.7taint tracking · 0.7high-level policy compilation · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information FlowabstractRuntime monitors detect vulnerabilities in embedded systems by running alongside untrusted software in order to detect violations of security policies as they occur, ideally with minimal overhead. Prior work has demonstrated language support for largely static security policies implemented using lattices and tag-based monitors. However, compiling high-level policies to modular hardware monitors that can implement a wide variety of security policies with minimal power has not been previously proposed. In this paper, we present a high-level security policy language, GARUDA, together with a compiler from GARUDA to Verilog, that enables the modular construction and composition of security hardware runtime monitors for a variety of security policies, including software fault isolation, secure control flow, and dynamic information flow via taint tracking. Unlike prior approaches in which the hardware monitors check all instructions, our hardware monitors are activated on-demand by the security policies which reduces the energy consumption. We perform experiments on Sniper, a full system multicore simulator, to evaluate the energy and performance tradeoffs of the security policies we have implemented so far. The policies are tested across a range of Splash-2 benchmarks. Seaghan Sefton, Taiman Siddiqui, Nathaniel St. Amour, Gordon Stewart 0001, Avinash Karanth |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |