Binary polynomial multipliers impact the overall performance and cost of elliptic curve cryptography (ECC) systems. Multiplication algorithms with subquadratic computational complexity are widely used to reduce area requirements and improve the delay of ECC cryptographic hardware. This work presents an elliptic curve scalar point multiplication (SPM) processor implementation using a novel classification of improved overlap-free multipliers targeting applications in the Internet of Things (IoT) devices. The proposed multipliers combine the advantages of fewer partial products and the overlap-free reconstructions which results in better recurrence and improved performance. The proposed multipliers and point multiplication hardware were designed, implemented, and tested on FPGA. The implemented processor presents a reasonable trade-off between speed and area consumption, and the design compares favorably with the previous designs in terms of area-delay product.

A new and efficient Hodgkin–Huxley (HH) neuron has been implemented on field-programmable gate array (FPGA). Multiplication, division, and exponential terms were implemented using the COordinate Rotation DIgital Computer (CORDIC) algorithm with carefully selected iteration numbers for each operation to greatly reduce the hardware resource requirements while simultaneously maintaining system throughput and a maximum clock frequency of over 275 MHz. The proposed design achieves higher modeling accuracy than previously proposed designs and an accuracy-resource trade-off that represents dramatic improvements. Additionally, all the neuron’s physiological parameters are variable as inputs to the proposed design postimplementation for a high degree of freedom in neuroscientific simulations. The implemented neuron is presented with results, and the behavior of the implemented system is evaluated to verify its close behavioral matching to the target neuron model.

Novel binary polynomial multipliers have been designed using M-term overlap-free Karatsuba multiplication (OFKM), where$M$is 5–8. The proposed designs were realized in digital hardware and implemented on field-programmable gate array (FPGA) and the best value of$M$was selected and presented for common National Institute of Standards and Technology (NIST) operand sizes from 64 to 571 bits. The implemented hardware designs use a hybrid approach that combines a given M-term overlap-free Karatsuba multipliers with two-term splitting to reduce the need for zero-padding in the final recurrent stages. Compared to the traditional M-term Karatsuba multipliers, the proposed overlap-free implementations offer reductions in delay and area-delay product (ADP). The proposed designs also compare favorably to previous implementations of binary polynomial multipliers. Their favorable characteristics make the proposed overlap-free Karatsuba polynomial multipliers viable options for use in cryptographic systems where speed is a significant consideration and hardware resource consumption must be limited.

The concept of input sparsity in Spiking Neural Networks for pattern recognition is introduced and explored with the goals of reductions in network inference time and size, leading to lower resource requirements in hardware implementations. A method is proposed by which selective input sparsity can be inferred from the training set to reduce the size of the network before training and decrease the network inference time. This method also requires no additional pre-processing steps during the testing phase, making it an excellent candidate for edge applications. For a basic fully connected spiking neural network trained to solve the MNIST handwritten digits, selective input sparsity is applied and the network size is reduced by 58.16% and a 41.07% decrease in the network's inference time is observed without notable accuracy hinderance. In the case of the Fashion MNIST dataset, selective input sparsity reduced the network size by 55.99% and reduced the network's inference time by 59.05%.

This work presents mathematical modifications to the Izhikevich Spiking Neuron Model to allow for a simple, low-area digital hardware implementation of a spiking neuron with similar behavioural characteristics and low computational intensity. The implemented neuron circuit only requires one input operational parameter to replicate all of the cortical neuron behaviours described by Izhikevich.

In this paper, a mixed-signal current-mode structure of a feed-forward neural network is implemented. In this network, neurons are divided and distributed as sub-neurons into parallel elements composing unified synapse-neuron building blocks in combination with the synapses. Although in this brief paper a resistive sigmoidal neuron is considered, the neuron is adaptable to other forms of transfer functions. The synapse structure employs AND gates in addition to weighted current mirrors to reduce the area of the design. As a proof of concept, a 4-3-2 CMOS-based network is implemented. The average and maximum power consumptions of the network are 0.93mW and 5.81 mW respectively. The area of the entire network is measured 142299.5μm2. The network was successfully tested with a series of sample patterns.