Analog circuit topology synthesis suffers from weak synthesis capability and low-synthesis efficiency, which result in a bottleneck toward its practical industrial applications. This article presents a proximal-policy-optimization-based circuit topology synthesis framework, which features a superior convergence rate. To further promote its synthesis efficiency, we have improved a deterministic optimization method by incorporating a bias-aware scheme and group concept, which is applied as a filter to eliminate the undesirable topologies in the early evaluation stage. Moreover, a graph-based refinement scheme is proposed to perform deterministically on the generated circuit topologies, which can efficiently add frequency compensation circuits. Compared with the state-of-the-art approaches, our proposed method not only boosts the synthesis efficiency by at least 3 times but also enhances the synthesis capability with a deterministic compensation scheme, showcasing significant advancement of performance efficacy.

Compared with conventional analog circuit topology synthesis methods, the deep-reinforcement-learning (DRL)-based method features much higher synthesis efficiency while possessing the merit of strong generalization capability. However, this method cannot synthesize operational amplifiers that involve signal division. To address this critical limitation, this article presents new synthesis rules to guide the DRL-based synthesis process. In addition, to meet various design specifications requested by users, we further develop a smart circuit synthesis system, which can robustly return a solution (i.e., a feasible circuit topology with detailed device sizes) right away as long as the input design specifications are reasonable. A transfer learning (TL) scheme is proposed to reduce the computation overhead of training this system. The experimental results show the efficacy of our smart circuit synthesis system and TL scheme, confirming an advancement over the state-of-the-art approaches.

This paper presents a novel deep-reinforcement-learning-based method for analog circuit structure synthesis. It behaves like a designer, who learns from trials, derives design knowledge and experience, and evolves gradually to eventually figure out a way to construct circuit structures that can meet the given design specifications. Necessary design rules are defined and applied to set up the specialized environment of reinforcement learning in order to reasonably construct circuit structures. The produced circuit structures are then verified by the simulation-in-loop sizing. In addition, hash table and symbolic analysis techniques are employed to significantly promote the evaluation efficiency. Our experimental results demonstrate the sound efficiency, strong reliability, and wide applicability of the proposed method.

Electron beam lithography (EBL) has been consolidated as one of the most common techniques for patterning at the nanoscale, especially below 22nm dimensions, thanks to its cost advantage over extreme ultraviolet lithography (EUL). Fogging effect, which always leads to pattern distortion in layout and in turn causes performance degradation, has been considered as a significant concern for wider adoption of EBL. In this work, we propose a reinforcement learning (RL) placement method that applies deep Q-learning to train a neural network as an agent. Different from the previous RL-based placement works, our proposed method uses a topological representation scheme that can advantageously render smaller search space in comparison to the currently popular absolute-coordinates-based representation (e.g., the state-of-the-art analytical placement method). To more effectively tackle mixed-signal ICs, our method focuses on the sensitive analog devices, which are better protected from potential variations due to fogging effects of other digital/analog portions. The experimental results show that our proposed placer is able to efficiently decrease the fogging effect variation among sensitive transistors in the analog portion up to 92%, while it is 13 times faster than the analytical RL-based placement

This article presents a novel deep-reinforcement-learning-based method for topology synthesis of analog-integrated circuits, especially operational amplifiers (OpAmps). It behaves like a human designer, who learns from trials, derives design knowledge and experience, and evolves gradually to finally figure out optimal manners to construct proper circuit topologies that meet design specifications. Essential design rules are defined and applied to set up the specialized environment for reinforcement learning in order to reasonably construct circuit topologies with building blocks as the basic components. Our proposed method can not only handle large-size circuit designs but also generate creative circuit topologies. The produced circuit topologies are verified by the simulation-in-loop sizing. In order to improve the evaluation efficiency, hash table and symbolic analysis techniques are utilized to significantly reduce the number of the produced topologies to be sized during the synthesis process. Compared with the state-of-the-art approaches, our proposed method significantly improves the synthesis efficiency by consuming only several hours on average to produce a trustworthy solution. Our experimental results demonstrate its sound efficiency, strong reliability, and wide applicability.

Fast and accurate performance estimation can significantly enhance the efficiency of automated analog circuit synthesis. This article presents a novel performance modeling method that can efficiently estimate circuit performance with ignorable model building overhead for variant circuit topologies. The proposed method starts with accurate transistor modeling by taking advantage of the advanced neural network (NN) fitting technique. It then utilizes the established transistor models and topology information from a circuit netlist to precisely discover the circuit dc operating point. Specialized deterministic schemes have been developed with the aid of an undirected bipartite graph converted from the circuit netlist. Moreover, the accurate NN transistor models help directly derive the small-signal model parameter values, which can be further applied to conduct symbolic analysis to evaluate circuit performances. Our experimental results not only compare various deterministic dc operating point computation schemes but also demonstrate the efficient model development, general applicability, speedy execution, and fair prediction of our proposed performance modeling method.

Automated analog circuit sizing is always a challenging task, due to high complexity involved, huge design space searched, and conflicting constraints traded off. This paper proposes an automated trial and error approach that combines reinforcement learning with deep learning for analog circuit sizing. Through the self-improvement learning way, the proposed method behaves like a designer, who learns from trials and derives experience, evolving itself to finally discover the sizes that satisfy the performance specification based on simulation results. In order to greatly reduce the number of simulations, we propose a symbolic filter that builds a polynomial equation system by utilizing the curve-fitting results and then applies the worked out small-signal parameter values to implement symbolic analysis to quickly evaluate the circuit performance, passing only the satisfied ones to the simulator. Our experimental results demonstrate the reliability of the proposed method, and also reveal the self-improvement capability.

This article presents an analog integrated circuit automated topology synthesis framework, where circuit topology synthesis can be efficiently realized by encoding circuit topology generation process as tree structure construction. Then the tree structures are decoded into circuit topologies. Our proposed method can not only handle large circuit designs but also generate creative topologies. To ensure only unique circuit topologies to be generated, two levels of isomorphism checks are performed at both tree structure level and circuit topology level. Then the generated un-sized circuit topologies are efficiently evaluated through a new method, which integrates topological symbolic analysis with gm/IDmethodology and curve-fitting technique. Along with the small-signal analysis, both linear and nonlinear programming techniques are utilized for topology feasibility checking. With only a small number of circuit topologies through the fast evaluation stage toward the subsequent detailed sizing and further evaluation, the efficiency of the whole circuit synthesis process can be significantly improved. The experimental results demonstrate high efficiency, strong reliability, and wide applicability of our proposed methods.

Automatically constructing analog circuit topology according to specifications is always a challenging task, due to the high complexity and substantial design expertise required. This paper proposes a graph-grammar-based method that can efficiently and automatically generate analog circuit topologies, which can be applied to general analog circuit synthesis frameworks for analog circuit design. The topology generation process is encoded by constructing a binary tree, in which the leaf nodes are decomposed according to a set of grammar rules. In order to guarantee only unique circuit structures to be generated, double isomorphism checks are applied at both tree structure level and circuit transistor level. Our experimental results demonstrate the high efficiency and wide applicability of the proposed method.

Evaluating the performance of schematic-level un-sized circuits is always a challenging task within the automated analog circuit synthesis process. One has to trade accuracy for efficiency in order to maintain efficient synthesis. This paper presents a new method of fast performance evaluation, which can be applied to general analog circuit synthesis frameworks. We propose to integrate graph-based symbolic analysis with the curve-fitting technique by using the gm/lDmethodology. Both linear programming and nonlinear programming are utilized to validate the feasibility of un-sized circuit topology with reference to the defined specifications. Our experimental results indicate high efficacy of the proposed method. It can significantly reduce the entire circuit synthesis time by leaving a small number of circuit topologies for detailed sizing and further evaluation.