Pun memes, which combine wordplay with visual elements, represent a popular form of humor in Chinese online communications.Despite their prevalence, current Vision-Language Models (VLMs) lack systematic evaluation in understanding and applying these culturallyspecific multimodal expressions.In this paper, we introduce PUNMEMECN, a novel benchmark designed to assess VLMs' capabilities in processing Chinese pun memes across three progressive tasks: pun meme detection, pun meme sentiment analysis, and chat-driven meme response.PUNMEMECN consists of 1,959 Chinese memes (653 pun memes and 1,306 non-pun memes) with comprehensive annotations of punchlines, sentiments, and explanations, alongside 2,008 multi-turn chat conversations incorporating these memes.Our experiments indicate that state-of-the-art VLMs struggle with Chinese pun memes, particularly with homophone wordplay, even with Chainof-Thought prompting.Notably, punchlines in memes can effectively conceal potentially harmful content from AI detection.These findings underscore the challenges in cross-cultural multimodal understanding and highlight the need for culture-specific approaches to humor comprehension in AI systems.

With the increasing integration of Multimodal Large Language Models (MLLMs) into the medical field, comprehensive evaluation of their performance in various medical domains becomes critical. However, existing benchmarks primarily assess general medical tasks, inadequately capturing performance in nuanced areas like the spine, which relies heavily on visual input. To address this, we introduce SpineBench, a comprehensive Visual Question Answering (VQA) benchmark designed for fine-grained analysis and evaluation of MLLMs in the spinal domain. SpineBench comprises 64,878 QA pairs from 40,263 spine images, covering 11 spinal diseases through two critical clinical tasks: spinal disease diagnosis and spinal lesion localization, both in multiple-choice format. SpineBench is built by integrating and standardizing image-label pairs from open-source spinal disease datasets, and samples challenging hard negative options for each VQA pair based on visual similarity (similar but not the same disease), simulating real-world challenging scenarios. We evaluate 12 leading MLLMs on SpineBench. The results reveal that these models exhibit poor performance in spinal tasks, highlighting limitations of current MLLM in the spine domain and guiding future improvements in spinal medicine applications. SpineBench is publicly available at https://zhangchenghanyu.github.io/SpineBench.github.io/.

Physical Ising machines have been shown to solve combinatoric optimization problems with orders-of-magnitude improvements in speed and energy efficiency o ver v on N eumann systems. However, building such a system is still in its infancy and a scalable, robust implementation remains challenging. CMOS-compatible electronic Ising machines (e.g., [1]) are promising as the mature technology helps bring scale, speed, and energy efficiency to the dynamical system. However, subtle issues can arise when using voltage-controlled transistors to act as programmable resistive coupling. In this paper, we propose a version of resistively-coupled Ising machine using quantized nodal interactions (QuBRIM), which significantly i mproved the predictability of the coupling resistor. The functionality of QuBRIM is demonstrated by solving the well-known Max-Cut problem using both behavioral and circuit level simulations in 45 nm CMOS technology node. We show that the dynamical system naturally seeks local minima in the objective function's energy landscape and that by applying spin-fix a nnealing, t he system reaches a global minimum with a high probability.

Ising machines and other nature-based computing platforms have recently become attractive due to their potential of outperforming conventional computers when solving problems that involve a large number of competing alternatives, such as combinatorial optimizations. In this paper, a newly proposed resistively-coupled Ising machine with bistable nodes (BRIM) is designed and simulated in a 45nm CMOS process. The performance of the proposed machine is evaluated based on its capability of solving the Max-cut graph problem. A spin-fix annealing technique is applied to help escape local minima and improve the solution quality. Simulation result shows that this technique effectively increases the probability of finding the Max-cut solution by 50.5% and reduces the solution error to 1.73 on average.

Physical Ising machines rely on nature to guide a dynamical system towards an optimal state which can be read out as a heuristical solution to a combinatorial optimization problem. Such designs that use nature as a computing mechanism can lead to higher performance and/or lower operation costs. Quantum annealers are a prominent example of such efforts. However, existing Ising machines are generally bulky and energy intensive. Such disadvantages may be acceptable if these designs provide some significant intrinsic advantages at a much larger scale in the future, which remains to be seen. But for now, integrated electronic designs of Ising machines allow more immediate applications. We propose one such design that uses bistable nodes, coupled with programmable and variable strengths. The design is fully CMOS compatible for on-chip applications and demonstrates competitive solution quality and significantly superior execution time and energy.

As the demand for better performance in terms of speed and power efficiency of the hardware increases because of the blooming industries such as the Internet of Things (IoT), the science and engineering tries to keep up. IoT is especially interested in faster interaction with the physical world at next to no cost, which is where the value of advancement in the field of A/D converters can be truly seen. Successive Approximation A/D converters (SA-ADC) have proven to be a solid solution for moderate speed and moderate resolution needs, at the same time consuming low power. However, the traditional SA-ADC needs N cycles to convert analog input signal to N-bit digital signal. Our proposed conversion method brings down the number of cycles to only one when configured properly, employing the concepts of oversampling and predicting the next value of the input signal. This can ultimately increase the speed of the SA-ADCs N-fold keeping the same power consumption, or even lower the power consumption when the signal has a narrow bandwidth. The proposed design is done with compatibility and cost-effectiveness in mind, so that it may be easily implemented in any currently existing SA-ADC designs.