This work demonstrates the benefit of spatial selectivity that a 4-element passive-beamforming continuous-time ADC can offer for the extreme dynamic range requirements in automotive radar. The beamforming-ADC is implemented in 40nm CMOS by R2R-based vector modulators as feed-in coefficients in combination with low-power implementations of a 4th-order inverter-based loop-filter, 4-bit asynchronous SAR-based quantizer and 4-bit current-steering feedback DACs. This work obtains >30dB of interferer suppression when deep notches are formed to obtain an effective spatial blocker dynamic range of 73.1dB. With notch-smoothing, the versatility to reduce the peak-to-notch-depth to 8dB for channel equalization is demonstrated. The beamforming-ADC consumes 7.3mW.

This paper proposes a self-corrected In- phase/Quadrature-phase (I/Q) digital Cartesian modulator. The modulator is comprised of double balanced Gilbert cells to mitigate code dependent input and output impedances. Transistor-level simulations in 28 nm bulk CMOS demonstrate a static error vector magnitude (EVM) of -35 dB at 79 GHz carrier while providing 9.5 dBm peak output power with ~19% drain efficiency. Transistor level analysis shows that the linearity is limited by the transconductance (gm) I and Q input code dependency. To address this dependency a self-contained 2-dimensional correction technique is proposed.The proposed correction method improves the EVM from -35 dB to -42.5 dB without compromising the output power, power efficiency and occupied silicon area. The proposed solution enables linear and power efficient transmitters (TXs) for mm-Wave applications.

This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a gm-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.