A sub-nanoliter, light-tolerant (780 µW/mm2), and power-adaptive forward-bulk optoelectronic microsystem for tetherless neural recording is presented. The CMOS bulk is used as a power harvester to utilize photogenerated carriers and a lower transistor threshold voltage for low power design (~0.3 µA at ~0.32 V). Increasing optical power boosts the system bandwidth to 14 kHz and the sampling frequency to 18.2 kHz, while maintaining the integrated input-referred noise (~10 µVRMS) stable, with an NEF of 2.34.

We present the elements of a pH-measuring autonomous microsystem, a Redox-Enabled Microscale Opto-Electronically Transduced Electrode (ReMOTE). The ReMOTE contains two electrodes of different materials, where the nearby$\mathbf{pH}$dictates the voltage between the two electrodes. The ReMOTE is a tetherless, all-optical microsystem which is powered and is transmitting its data optically. The ReMOTE is designed in a 180 nm CMOS SOI process, occupies merely$\mathbf{417}\ \mu \mathbf{m}\times \mathbf{48}\ \mu \mathbf{m}$, and it only consumes$\mathbf{2}\ \mu\mathbf{W}$. For the functional verification, we have conducted pH measurements using a thin film titanium nitride working electrode and a Ag/AgCl reference electrode, of which the voltage per pH sensitivity was 42.53 mV/pH.

Single-photon avalanche diode (SPAD) based LiDAR is becoming the de-facto choice for 3D imaging in many emerging applications. However, they suffer from three significant limitations: (a) the additional time-of-arrival dimension results in a data throughput bottleneck, (b) limited spatial resolution due to either low fill-factor (flash LiDAR) or scanning time (scanning-based LiDAR), and (c) coarse depth resolution due to quantization of photon timing by existing SPAD timing circuitries. In this paper, we present a novel, in-pixel computing architecture that we term first arrival differential (FAD) LiDAR, where instead of recording quantized time-of-arrival information at individual pixels, we record a temporal differential measurement between pairs of pixels. FAD captures relative order of photon arrivals at the two pixels (within a cycle or laser period) and creates a one-to-one mapping between this differential measurement and depth differences between the two pixels. We perform detailed system analysis and characterization using Monte Carlo simulation, and experimental emulation using a scanning-based single-photon avalanche diode. FAD pixels can result in a 10–100x reduction in per-pixel data throughput compared to TDC-based pixels. Under the same bandwidth constraints, FAD-LiDAR achieves better depth resolution and/or range than several state-of-the-art TDC-based LiDAR baselines.

We propose a scalable architecture for a differential single-photon avalanche diode (D-SPAD) array which generates measurements based on differential time-of-arrival in lieu of absolute time-of-arrival. This design addresses the throughput bottleneck in conventional sensors that record time-of-arrival statistics (such as histograms or raw arrival-time data) directly. In addition, this design also mitigates saturation at the pixel level and at the counter, making it an ideal candidate for use when the scene being imaged covers a high dynamic range (HDR). The differential nature of the data also obviates the need for large digital circuitry such as high bit depth counters or time to digital converters (TDCs). A prototype test structure of 16 pixels was fabricated in 0.18 $\mu$m CMOS, and we show images reconstructed from this chip that illustrate its capabilities.

A novel method for a two way offset calibration for an interleaved 2bit/cycle SAR based ADC is proposed. The offset mismatch between the interleaved sub-ADCs is cancelled using a background calibration circuit. Using the same circuit, the offset mismatch between the comparators used in the 2-bit per cycle SAR based sub-ADC's are cancelled at the same time. The technique is realized using a Reference comparator that sets the target offset for all comparators in all sub-ADCs. Using the proposed technique, a 1 GS/s 6-bit 2b/cycle SAR ADC is designed in 65 nm CMOS technology. The ADC consumes 3.36 mW from a 1.2 V supply voltage and achieves signal-to-noise-and-distortion ratio (SNDR) of 37.41 dB and figure of merit (FoM) of 55.49 fJ/Conv.Step at Nyquist frequency input. The FoM with mean SNDR derived from Monte-Carlo simulation is 60.42 fJ/Conv.Step. The proposed technique offers 4.5 dB improvement on average over a non-calibrated SAR ADC based on 1000 Monte-Carlo simulations.