The standard-cell methodology has become the dominant paradigm in modern VLSI design due to its scalability and reusability. However, optimizing individual cells in isolation often yields suboptimal design-level results. Breaking the rigid abstraction of standard cells enables fine-grained optimization opportunities such as diffusion sharing and direct connections through gate or metal-to-diffusion layers, particularly in advanced technologies. Prior work on pure transistor-level placement without standard-cell abstraction has faced scalability challenges for larger designs. A practical alternative is to use standard-cell placement as an initial legal transistor placement and refine it locally at the transistor level. Furthermore, the existing transistor-level routing framework overlooks escape pin locations, leading to excessive upper-layer routing demand. To address these limitations, this paper presents TransOpt, a transistor-level optimization framework that refines standard-cell placements through local transistor-level placement refinement and escape-net-HPWL-aware routing optimization. Experimental results on benchmarks using the open-source 3 nm GT3 PDK demonstrate the effectiveness of the proposed transistor-level optimization techniques, achieving significant reductions in wirelength and via count compared with standard-cell baselines.

In advanced technology nodes, benefits from scaling have become limited in terms of power, performance, and area (PPA), necessitating improvements through design-technology cooptimization (DTCO). While the standard-cell methodology is widely used in modern VLSI design, it inherently constrains the potential of DTCO due to its abstraction at the logic level, limiting optimization at the physical level. To bridge this gap, transistor-level design methodology is desired to break the abstraction of standard cells. Existing research has explored large-scale transistor placement, but a gap remains in developing a routing framework that efficiently addresses transistor-level routing challenges. This paper proposes a pioneering transistorlevel routing framework for large-scale transistor placements, along with an efficient CP-SAT (Constraint ProgrammingSATisfiability) formulation for routing in lower layers. Experimental results demonstrate that the proposed routing framework enables transistor-level designs to achieve significantly reduced total wirelength and high utilization rates for designs with hundreds to thousands of transistors, outperforming traditional standard-cell-based approaches in advanced technology nodes.

The standard-cell methodology is widely adopted in the VLSI design flow due to its scalability, reusability, and compatibility with electronic design automation (EDA) tools. However, the fixed positions and confinement of PMOS and NMOS transistors within its standard cell layout impose limitations on overall wirelength and area optimization. Directly placing individual transistors in a design can provide greater flexibility to explore more diffusion-sharing opportunities, which can potentially result in less wirelength and areas than standard-cell-based designs. Unfortunately, existing transistor placement approaches are limited to a very small scale, e.g., a single standard cell. This paper presents TransPlace, the first transistor-level placement framework that is capable of handling a large number of transistors while considering the overall diffusion sharing and wirelength optimization. Experimental results demonstrate its effectiveness in minimizing wirelength and reducing design area beyond the limits of standard-cell-based designs.

Despite significant recent advancements in analog design automation, analog front-end design remains a challenge characterized by its heavy reliance on human designer expertise together with extensive trial-and-error simulations. In this paper, we present a novel data-driven analog circuit synthesizer with automatic topology selection and sizing. We propose a modular approach to build a comprehensive, parameterized circuit topology library. Instead of starting from an exhaustive dataset, which is often not available or too expensive to build, we build an adaptive topology dataset, which can later be enhanced with synthetic data generated using variational autoencoders (VAE), a generative machine learning technique. This integration bolsters our methodology's predictive capabilities, minimizing the risk of inadvertent oversight of viable topologies. To ensure accuracy and robustness, the predicted topology is re-sized for verification and further performance optimization. Our experiments, which involve over 360 OPAMP topologies and over 540K data points demonstrate our framework's capability to identify optimal topology and its sizing within minutes, achieving design quality comparable to that of experienced designers.

Topological quantum error correction (TQEC) is promising for scalable fault-tolerant quantum computation. The required resource of a TQEC circuit can be modeled as its space-time volume of a three-dimensional geometric description. Implementing a quantum algorithm with a reasonable physical qubit number and computation time is challenging for large-scale complex problems. Therefore, it is desirable to minimize the space-time volume for large-scale TQEC circuits. Previous work proposed bridge compression, which can significantly compress a TQEC circuit, but it was performed manually. This article presents the first automated tool that can perform bridge compression on a large-scale TQEC circuit. Our proposed algorithm applies the bridge compression technique to compactify TQEC circuits with modularization. Besides, we offer a time-ordering-aware 2.5-D placement for compacting TQEC circuits and satisfying time-ordered measurement constraints. On the other hand, we suggest friend net-aware routing to effectively reduce the required routing resource under topological deformation. Compared with the state-of-the-art work, experimental results show that our proposed algorithm can averagely reduce space-time volumes by 84%.

The topological quantum error correction (TQEC) scheme is promising for scalable and reliable quantum computing. A TQEC circuit can be modeled by a three-dimensional diagram, and the implementation resource of a TQEC circuit is abstracted to its space-time volume. Implementing a quantum algorithm with a reasonable physical qubit number and reasonable computation time is challenging for large-scale practical problems. Therefore, minimizing the space-time volume of a TQEC circuit becomes a crucial issue. Previous work shows that bridge compression can greatly compress TQEC circuits, but it was performed only manually. It is desirable to develop automated compression techniques for TQEC circuits to achieve low-overhead, large-scale quantum computations. In this paper, we present the first work that can automatically perform bridge compression on TQEC circuits. Compared with the state-of-the-art method, experimental results show that our proposed algorithm can averagely reduce space-time volumes by 83%.

As clock frequencies increase, topology-matching bus routing is desired to provide an initial routing result which facilitates the following buffer insertion to meet the timing constraints. In this article, we present a complete topology-matching bus routing framework considering nonuniform track configurations. In the framework, a bus clustering technique is proposed to reduce the routing complexity by grouping buses sharing similar pin locations. To perform topology-matching routing in a nonuniform track configuration, we propose a directed acyclic graph-based algorithm to connect a bus in a specific topology. Furthermore, a rip-up and reroute scheme is applied to alleviate the routing congestion. Compared with the state-of-the-art topology-matching bus routers, our proposed algorithm significantly improves the routing quality and reduces the number of spacing violations in comparable runtime.

As clock frequencies increase, topology-matching bus routing is desired to provide an initial routing result which facilitates the following buffer insertion to meet the timing constraints. Our algorithm consists of three main techniques: (1) a bus clustering method to reduce the routing complexity, (2) a DAG-based algorithm to connect a bus in the specific topology, and (3) a rip-up and re-route scheme to alleviate the routing congestion. Experimental results show that our proposed algorithm outperforms all the participating teams of the 2018 CAD Contest at ICCAD, where the top-3 routers result in 145%, 158%, and 420% higher costs than ours.

Detailed routing is the most complicated and time-consuming stage in VLSI design and has become a critical process for advanced node enablement. To handle the high complexity of modern detailed routing, initial detailed routing is often employed to minimize design-rule violations to facilitate final detailed routing, even though it is still not violation-free after initial routing. This paper presents a novel initial detailed routing algorithm to consider industrial design-rule constraints and optimize the total wirelength and via count. Our algorithm consists of three major stages: (1) an effective pin-access point generation method to identify valid points to model a complex pin shape, (2) a via-aware track assignment method to minimize the overlaps between assigned wire segments, and (3) a detailed routing algorithm with a novel negotiation-based rip-up and re-route scheme that enables multithreading and honors global routing information while minimizing design-rule violations. Experimental results show that our router outperforms all the winning teams of the 2018 ACM ISPD Initial Detailed Routing Contest, where the top-3 routers result in 23%, 52%, and 1224% higher costs than ours.