Won Joon Choi

dblp:229/6660 · DBLP profile ↗
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4ranked-venue papers
1as first author
3since 2021 · last 2026
0009-0008-9769-9263ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Applied, interdisciplinary, general and emerging computing · 1
YearPublicationVenuePosition
2026 A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation
abstract
We propose a UNet-based foundation model and its self-supervised learning method to address two key challenges: 1)lack of qualified annotated analog layout data, and 2)excessive variety in analog layout design tasks. For self-supervised learning, we propose random patch sampling and random masking techniques automatically to obtain enough training data from a small unannotated layout dataset. The obtained data are greatly augmented, less biased, equally sized, and contain enough information for excessive varieties of qualified layout patterns. By pre-training with the obtained data, the proposed foundation model can learn implicit general knowledge on layout patterns so that it can be fine-tuned for various downstream layout tasks with small task-specific datasets. Fine-tuning provides an efficient and consolidated methodology for diverse downstream tasks, reducing the enormous human effort to develop a model per task separately. In experiments, the foundation model was pre-trained using 324,000 samples obtained from 6 silicon-proved manually designed analog circuits, then it was fine-tuned for the five example downstream tasks: generating contacts, vias, dummy fingers, N-wells, and metal routings. The fine-tuned models successfully performed these tasks for more than one thousand unseen layout inputs, generating DRC/LVS-clean layouts for 96.6% of samples. Compared with training the model from scratch for the metal routing task, fine-tuning required only 1/8 of the data to achieve the same dice score of 0.95. With the same data, fine-tuning achieved a 90% lower validation loss and a 40% higher benchmark score than training from scratch.
Sungyu Jeong, Won Joon Choi, Junung Choi, Anik Biswas, Byungsub Kim
IEEE Trans. Circuits Syst. I Regul. Pap.2
2025 An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses
abstract
Determining a channel’s characteristics is a fundamental step for designing a high-speed link system. By identifying the properties of the channel, designers can gain insights into how to transmit a signal with low distortion and optimize a transceiver’s architecture. As the channel’s characteristics can be identified by analyzing its single-bit pulse response (PR), obtaining an accurate PR plot is critical for reliable channel characterization. Therefore, it is preferred to measure the PR in situ to minimize the parasitic effects. In this work, we introduce a novel approach for measuring PR in situ, designed to quickly and accurately generate undistorted plot results. To prove the efficacy of the proposed method, we designed an on-chip sampling scope circuit and fabricated a test chip in 28-nm CMOS technology. While being able to measure a distortion-free PR, the proposed method demonstrates a more than$10^{5}$times faster pulse acquisition rate than prior arts.
Won Joon Choi, Myungguk Lee, Junung Choi, Jaeik Cho, Gain Kim, Byungsub Kim
IEEE Trans. Very Large Scale Integr. Syst.1
2024 Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links
abstract
This paper presents compact single-ended wireline transceivers with software-generated receiver front-ends. The developed software framework significantly shortens the physical design time of 1/N-rate wireline receiver front-ends. The physical layouts of various receiver front-ends were software-generated in four different CMOS technology nodes (28 nm, 40 nm, 65 nm, and 90 nm) with four different front-end architectures targeting various data rates. In the post-layout simulation, the receiver front-ends generated within a second by the software achieved nearly the same performances as the manually-designed receiver front-ends that require more than about 30 hours of design time. For demonstration, we generated 8 Gb/s full-rate, 10 Gb/s half-rate, 12 Gb/s, and 20 Gb/s quarter-rate receiver front-ends, and fabricated them with a manually-designed feed-forward equalization transmitter in 28 nm CMOS process. The transceivers were measured with the data rate up to 20 Gb/s while consuming 1.39 pJ/b at the channel loss of −9.2 dB. The transceiver with software-generated receiver achieved the highest data rate per area as well as the smallest area among the relevant prior arts while reducing the physical design time of the receiver front-end by more than 140,000 times.
Myungguk Lee, Jaeik Cho, Junung Choi, Won Joon Choi, Jiyun Lee, Iksu Jang, Changjae Moon, Gain Kim, Byungsub Kim
IEEE Trans. Circuits Syst. I Regul. Pap.4
2018 Monitoring Atmospheric Composition by Geo-Kompsat-2: Goci-2, Ami and Gems
abstract
Monitoring of aerosol optical properties in high temporal and spatial resolution has been realized with the launch of Geostationary Ocean Color Imager (GOCI) and Meteorological Imager (MI) onboard the Communication, Oceanography, and Meteorology Satellite (COMS), also known as GEO-KOMPSAT (GK)-1 in 2010. In 2018, Advanced MI (AMI) will be launched with further enhanced capability onboard the GK-2A. GOCI-2 onboard GK-2B is planned to be launched in late 2019-early 2020 with Geostationary Environment Monitoring Spectrometer (GEMS). GEMS is a UV-visible spectrometer to monitor column concentration of trace gas including O3, NO2, SO2and HCHO, for the first time in high temporal and spatial resolution. In this study, results and plan to monitor atmospheric composition from geostationary earth orbit(GEO) are presented.
Jhoon Kim, Myungje Choi, Mijin Kim, Hyungwang Lim, Seovouna Lee, Kyung Jung Moon, Won Joon Choi, Jong Min Yoon, Sang-Kyoon Kim, Dai Hn Ko, Youngje Park, Chu-Yong Chung
IGARSS7