Non-idealities of the track-and-hold (T&H) circuit in analog-to-digital converters (ADCs) can severely limit the ADC linearity. In practical applications, traditional calibration techniques are ineffective in suppressing these effects due to the multi-dimensional dependency of the non-idealities on e.g., input voltage, frequency and temperature. To address this, we propose a calibration solution that combines circuit knowledge of the error mechanisms with a data-driven approach into a shallow neural network (NN) containing just 5 neurons. Due to the small size of the NN, the output of the network can be interpreted and referred back to the underlying circuit non-idealities improving the predictability and reliability of the model. The effectiveness of the NN-based calibration is verified on silicon measurements of 10 different 12-bit SAR ADC samples manufactured in a 65nm CMOS technology, demonstrating an average improvement up to 6.8dB and 13.3dB on the measured SNDR and SFDR, respectively. To the best of the author’s knowledge, this is the first demonstration of a compact, interpretable NN-based calibration solution tested over amplitude, frequency, and temperature for multiple samples, while maintaining physics-based insight into the correction process.

The linearity of Sigma Delta Modulators (SDMs) is evaluated performing a Fourier Transform of the output bitstream. The presence of quantization noise complicates this task: many samples and lengthy simulations are needed to lower this noise floor and evaluate the signal harmonics. We present here a method to estimate the quantization noise, remove it from the SDM bitstream, and enable the reduction of the samples needed to evaluate the SDM linearity. By applying the proposed technique to a Simulink®model of a 4th-order SDM, the accuracy of the linearity estimation is kept unchanged using 5000x less bitstream samples. This method enables a significant reduction of SDM verification time that in turn can be used to improve the statistical coverage of design over parameter variability.

In this work, a rapid method is developed for predicting device-level temperature shifts in electronic and photonic integrated circuits. The method models the most dominant thermal interactions through resistive star networks. The resistance values are obtained through interpolation of data acquired by a finite element method solver or experimental characterizations and can be used to predict all device temperatures. Simulations using COMSOL and measurements of a silicon IC have verified the key assumptions of the method. After calibrating the method with experimentally obtained thermal reference data, thermal estimations have been shown to be as close as 8.1% to measurements. Compared to a finite element based approach, the method can allow for a 1 to 2 orders of magnitude speed-up, which the user may choose to trade off for a higher estimation accuracy.

This paper presents a high impedance, low noise, and low offset Analogue Front-End (AFE) designed to readout biosignals using non-contact electrodes. The circuit is fabricated in an amorphous InGaZnO (a-IGZO) technology. An autozeroing technique is used to reduce both 1/f noise and AFE offset while minimizing the charge required from the input, leading to a high input impedance. The AFE circuit makes use of two voltage buffers operated in a ping-pong configuration to ensure a continuous time operation. Measurement results reveal that, when autozeroing each 100μs, the AFE input impedance reaches 250MΩ at 50Hz, which is about 6x larger compared to the current state-of-the-art in large-area electronics. The Signal-to-Noise ratio estimated for non-contact electrodes with a 200MΩ series impedance remains above 20dB, while achieving a bandwidth of 1kHz, a power consumption of 0.22mW and an area per channel of 2.94mm2. Thanks to its versatility, the proposed AFE architecture in combination with the mechanical properties offered by the TFTs on foil, can be exploited to develop a new generation of wearable patches that are conformable, lightweight, and cost-effective. These devices could be employed in home health-monitoring applications to acquire biosignals such as sEMG (surface electromyography), while providing a great level of comfort to the patient.

In this work is presented a low-noise Charge Sensitive Amplifier (CSA) suitable for the readout of high-impedance pyroelectric sensors. The circuit exploits a novel Correlated Double Sampling (CDS) technique which allows both continuous-time integration and cancellation of the Thin-Film Transistor (TFT) 1/f noise. The CSA has been implemented in a printed unipolar Organic TFT technology and simulation results demonstrate a Signal-to-Noise Ratio (SNR) improvement of approximately 10 dB when the proposed CDS technique is applied at the frequency of 500 Hz. This result is expected e.g., to extend the proximity detection range and improve the safety in human-machine applications using large-area infrared-sensing surfaces. Moreover, the proposed technique can be used in generic Analog Frontend Electronics embedding switched capacitor amplifiers, to suppress correlated noise sources.

A Process Design Kit (PDK) for gravure-printed Organic Thin-Film Transistor (OTFT) technology is presented in this paper. The transistor model developed in the PDK enables an accurate prediction of static, dynamic and noise performance of complex organic circuits. The developed Electronic Design Automation (EDA) tools exploit an adaptive strategy to improve the versatility of the PDK in relation to the advancements of the manufacturing process. The design and experimental characterization of a Charge Sensitive Amplifier is used to demonstrate the effectiveness of the PDK. The availability of a versatile and accurate Process Design Kit is expected to enable a reliable design process for complex circuits based on an organic printed technology.