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Lance M.-T. Lan

dblp:23/1000 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 88% Embedded and real-time systems · 12%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › task allocation
module allocation
0.011987
Task Allocation and Precedence Relations for Distributed Real-Time Systems · IEEE Trans. Computers 1987
Parallel and multicore computing
task allocation
0.011987
Task Allocation and Precedence Relations for Distributed Real-Time Systems · IEEE Trans. Computers 1987
Embedded and real-time systems
distributed real-time systems
0.011987
Task Allocation and Precedence Relations for Distributed Real-Time Systems · IEEE Trans. Computers 1987
Parallel and multicore computing › task scheduling
precedence constraints
0.011987
Task Allocation and Precedence Relations for Distributed Real-Time Systems · IEEE Trans. Computers 1987

Methods — techniques the papers use, named apart from their topics

simulation · 0.0analytical modeling · 0.0
YearPublicationVenuePosition
1987 Task Allocation and Precedence Relations for Distributed Real-Time Systems
abstract
In a distributed processing system with the application software partitioned into a set of program modules, allocation of those modules to the processors is an important problem. This paper presents a method for optimal module allocation that satisfies certain performance constraints. An objective function that includes the intermodule communication (IMC) and accumulative execution time (AET) of each module is proposed. It minimizes the bottleneck-processor utilization—a good principle for task allocation. Next, the effects of precedence relationship (PR) among program modules on response time are studied. Both simulation and analytical results reveal that the program-size ratio between two consecutive modules plays an important role in task response time. Finally, an algorithm based on PR, AET, and IMC and on the proposed objective function is presented. This algorithm generates better module assignments than those that do not consider the PR effects.
Wesley W. Chu, Lance M.-T. Lan
IEEE Trans. Computers2