This article presents a 56-Gb/s distributed feedback (DFB) laser driver integrated with a PAM-4 clock and data recovery (CDR). A mixed-signal digital-to-analog converter (DAC) is adopted for power-efficient linear driving. With the help of the CDR, high-speed PAM-4 input is digitized into thermometer code, which is processed in NRZ format along the data path before summation at the output node. In this way, higher modulation linearity is realized by independently adjusting the weight of each slice. A dc-coupled differential drive stage is devised to improve signal integrity and energy efficiency at high speed. Employing a fractional-UI delay asymmetric feed-forward equalization (FFE) extends the laser’s bandwidth while the nonlinearity is compensated. The proposed driver is fabricated in 28-nm CMOS and co-packaged with a DFB laser diode. Measurement results show the modulated optical output reaches a 56-Gb/s data rate and consumes 353-mW power, thus corresponding to the energy efficiency of 6.3 pJ/bit, including the integrated CDR.

This paper presents a 32Gb/s non-return-to-zero (NRZ) distributed feedback (DFB) laser diode driver (LDD) fabricated in 65nm CMOS. The driver is directly wire-bonded to the laser diode without AC-coupling capacitors, which simplifies the packaging and ensures high bandwidth (BW). To improve power efficiency, the active back-termination (ABT) structure is employed to absorb signal reflections with lower power. A continuous time linear equalizer (CTLE), a 3-stage current mode logic (CML) buffer and a pre-driver are employed to compensate the channel loss and achieve a bandwidth extension by providing an estimated gain boosting of 7.5dB at high frequency. The clear electrical eye-diagram of the driver is obtained beyond 40Gb/s, while the measured optical transmission data-rate can still exceed 32Gb/s with a rms-jitter of 2ps. According to the experimental results, the bias current and modulation current of the driver are 40mA and 40mApp, respectively, where the power consumption is 390mW.

A 800G integrated silicon-photonic transmitter is presented, including a 16-channel photonic integrated chip (PIC) and two electrical chiplets (EICs) that are realized based on an arrayed travelling wave dual-drive Mach-Zehnder modulator (MZM) and two 8-channel CMOS drivers. The proposed multi-channel PIC is fabricated on a high-resistance silicon-on-insulator (SOI) wafer with a 220 nm thick silicon layer and a$\mathbf{2}\ \boldsymbol{\mu} \mathbf{m}$thick buried oxide (BOX) using the foundry-ready CMOS process, while the drivers are implemented in a standard$\mathbf{65}\mathbf{nm}$CMOS process. The driver employs a combination of distributed architecture, 2-tap feedforward equalization (FFE) and push-pull output stage, experimentally exhibiting an averaged bandwidth higher than 28.5GHz and a differential swing of 4.0Vpp on$\mathbf{50}\mathbf{\Omega}$load, respectively. The 50Gb/s electrical eye-diagram is measured with 1.41ps rms-jitter, while the optical extinction ratio (ER) exceeds 3.0dB with 5.35pJ/bit power efficiency.

This paper presents a 50-Gb/s optical receiver (ORX) chipset, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit in a 45-nm silicon-on-insulator CMOS. The proposed inverter-based TIA employs hybrid shunt-series peaking inductors to extend the bandwidth (BW). A baud-rate CDR is proposed to reduce the sampling phases and clocking power by half. To optimise the ORX for in- package integration, a compact-size digital loop is adopted in each channel, and the clock is recovered by phase interpolation from a shared reference. A complete optical-to-electrical (OE) link is built by integrating the proposed ORX with a high-speed Silicon Photonics (SiP) photodetector (PD). Measurements show that the proposed TIA has a transimpedance gain of 53 dB$\Omega $and a BW of 27 GHz. By integrating it with the SiP PD, the OE front-end (PD+TIA) achieves an input sensitivity of −7.7 dBm at 50 Gb/s and BER$ < 10^{-12}$. It features a power efficiency of 1.61 pJ/bit at a data rate of 64 Gb/s. The complete 50 Gb/s ORX achieves data recovery at a quarter rate of 12.5 Gb/s with an output jitter of 1.6 psrms, and has a 3.125 GHz clock with phase noise of −115.22 dBc/Hz at an offset frequency of 1 MHz.

This paper presents a hybrid-integrated optical transceiver front-end for beyond-400G short-reach optical links. A pair of the monolithic 8-channel laser drivers and the trans-impedance amplifier (TIA) is developed in 180nm SiGe BiCMOS, incorporating arrayed Vertical-Cavity-Surface- Emitting Lasers and photo-detectors. The driver uses a$2^{\mathrm {nd}}$-order continuous-time linear equalizer (CTLE) to compensate for the channel loss with a nonlinear frequency response. Both the inductive peaking and RC-degeneration are embedded at the output stage to extend the optical modulation bandwidth (BW). The series-peaking and multi-stage distributed CTLE are combined in a resistive feedback TIA topology for improved BW and linearity. Measurement results show up to 100-Gb/s PAM-4 electrical eyes of the driver and TIA. The optical transmitter front-end operates 56 Gb/s, 4.1-dB extinction ratio, and 6.6-pJ/bit power efficiency, while the optical receiver front-end achieves 56-Gb/s,$10^{-6}$bit error rate, and 5.9-pJ/bit power efficiency.

This article presents a reconfigurable silicon- photonics transmitter (TX) for short-reach optical interconnects. The proposed hybrid-integrated TX combines a 65-nm CMOS driver with a 180-nm SOI-CMOS silicon-photonic Mach-Zehnder Modulator (MZM). The driver integrated with in- segment fractional-UI spaced feed-forward equalizer (FFE) is proposed to support the non-return-zero (NRZ) signaling, electrical- and optical-domain 4-level pulse-amplitude modulation (PAM-4) signaling. The driver employs a reconfigurable distributed topology to achieve high swing, wide bandwidth and flexible operation. The MZM is driven differentially in a push-pull configuration for high modulation efficiency. Measurement results show that the proposed TX operates up to 50-Gb/s NRZ data rate with 4-Vppd swing and 1.92-ps RMS jitter. In the optical PAM-4 mode, it reaches 56-Gb/s data rate and achieves >5-dB extinction ratio (ER) at the cost of 10.9-pJ/bit power efficiency.

In this paper, we present a linear optical receiver for 112-Gb/s PAM-4 optical link. We propose a transimpedance front-end that optimizes thermal noise, power supply noise rejection, linearity and bandwidth altogether. The pseudo-differential structure is employed to achieve both low thermal noise and good power supply noise rejection. A transimpedance amplifier (TIA) gain control technique is proposed to improve linearity at both topology and transistor level while maintaining stability. An NIC-CTLE combo extends bandwidth with optimized frequency response. Designed in a 130nm SiGe BiCMOS process, the receiver realizes 37 GHz total bandwidth and input-referred noise of 19.8 pA/√Hz. The transimpedance gain can vary from 70 dB Ω to 50 dBΩ, which enables maximum input overload current of 1.8 mApp with <; 5% THD at differential output swing of 600 mVpp. The receiver consumes 77mA from 3.3V supply.

A 50Gb/s PAM-4 optical receiver with Silicon Photonic (Si-Ph) photodiode (PD) and CMOS linear transimpedance amplifier (TIA) is presented. To optimize both noise and bandwidth, a two-stage front-end architecture-a high gain-low bandwidth TIA followed by a two-stage continuous time linear equalizer (CTLE) is adopted. Gain adjustment of the entire link is achieved by adjusting the TIA feedback resistor and the voltage of variable gain amplifier (VGA) to ensure that the receiver analog front-end (AFE) remains linear over the entire photocurrent input range. The chip has been realized in 40nm CMOS process. Experimental results show the TIA achieves 66dBΩ transimpedance gain, 24.4GHz bandwidth, 20dB gain dynamic range, maximum overload current 2mA, and differential output swing of 400mV. The total power consumption of the chip is 125.4mW.

A dual-mode second-order reconfigurable quadrature bandpass continuous-time delta-sigma modulator is presented for a low-IF global navigation satellite system receiver to simplify the entire architecture. The proposed modulator is capable of supporting both narrowband of 5-MHz bandwidth (BW) and wideband of 20-MHz BW. An amplifier topology with active feed-forward and antipole-splitting compensation schemes is proposed. The flexible amplifiers in active-RC integrators and preamplifiers in comparators are implemented with power scaling technique to effectively adjust the power consumption for both BWs. A 1-bit digitally switched current digital-toanalog converter structure with gate-leakage compensation and low-latency dynamic element matching is proposed to cover large current variations and mitigate the gate-leakage issue. Digital I/Q self-calibration algorithm is realized to improve the imagerejection ratio (IRR). Implemented in 65-nm CMOS, the ΔΣ modulator achieves 67.8-/61.4-dB dynamic range, 65.9-/53.7-dB signal-to-noise-plus-distortion ratio, and >60-dB IRR after calibration across 5-/20-MHz BW with center frequencies of 4/12 MHz, respectively. Powered by a 1.2 V supply, the modulator only consumes 4.2/8.1 mW, resulting in measured figure-of-merits of 0.26/0.51 pJ/conversion step.

A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers is presented. The baseband circuit consists of an I/Q calibration circuit, a reconfigurable complex band-pass filter (C-BPF) and an AGC loop. It provides I/Q mismatch auto-calibration with the aid of a FPGA. The 3rd/ 5th-order reconfigurable C-BPF supports various bandwidths from 2.2 to 10 MHz and with different center frequencies from 3.996 to 16 MHz. The AGC loop features 5-50 dB gain range and 1 dB step, and digital AGC algorithms. The auto DC-offset cancellation is also integrated on-chip. The analog baseband circuit has been implemented in 180 nm CMOS and consumes 6.5-13 mA variable current thanks to the power scaling technique. The measured image-rejection ratio is 45-55 dB, improved by 22 dB after I/Q calibration.

This paper presents a 65nm multi-mode complex band-pass filter (C-BPF) used in low-IF GNSS receivers. It supports the bandwidth of 4MHz, 10MHz and 18MHz, and can be centered at 4.2MHz, 6.1MHz, 12.3MHz and 28MHz. The OTAs served in the filter are realized in arrays which makes the power consumption scalable among different operation modes. In addition, assistant transconductors (assistant-gm) are adopted to compensate the outputs of each OTA stage, which in turn saves at maximum 9mA DC current for the whole filter. In order to achieve higher than 30dB image rejection ratio (IRR), another group of assistant-gms are introduced to the input stage for I/Q mismatch calibration, which is able to regulate a maximum ±3dB amplitude imbalance and ±5° phase imbalance. The filter consumes less than 10mA in the 28MHz-IF, 18MHz-bandwidth mode, and achieves >31dB IRR with the maximum I/Q amplitude and phase mismatch.

This paper presents a power detection based I/Q imbalance self-calibration technique to compensate signal path gain and phase mismatch in a reconfigurable low-IF receiver. The calibration can be carried out at startup to improve the image rejection ratio (IRR) of the IF complex-bandpass filter, and then configuration words are saved. The system employs an analog I/Q calibration module to adjust signal path gain and phase mismatch, a power detector to measure I/Q imbalances, digital circuits to implement the calibration algorithm, and a digital AGC to adjust IF signals within a predetermined level. The self-calibration system is implemented as a part of a multi-mode GNSS (Global Navigation Satellite Systems) receiver. Only one 2-bit ADC in I (or Q) path is needed to sample the analog IF signal. Measurement results show that the calibrated IRR achieves an average of 50dB in different operation modes which gets a 10~20dB improvement. The low-IF GNSS receiver is fabricated in 65nm CMOS process, and the digital part of the self-calibration system is implemented in a FPGA.