This article presents a fully passive noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) that can be compatible with dynamic voltage and frequency scaling (DVFS) schemes while offering a 12-bit resolution for Internet-of-Things (IoT) sensor applications. To realize a voltage-scalable suppression of the in-band quantization noise, the proposed ADC utilizes a second-order cascade of integrators with feedforward (CIFF) NS loop with a 3-input dynamic comparator, which can obtain an additional resolution of more than 3 bits. A cyclic dynamic element matching (CDEM) for MSB is seamlessly combined with the NS operation and simply realized by shift registers (SRs). The MSB CDEM reduces dominant in-band harmonic distortions due to capacitor mismatch by not only averaging out but also randomizing the MSB mismatch errors with modulation dither from the CIFF NS loop. In addition, a last-bit majority voting (LMV) technique is applied when resolving the LSB to reduce the comparator noise by half with four additional cycles. With both the LMV and CDEM techniques enabled, the SNR and SNDR are enhanced to 73.3 and 72.3 dB, respectively. The ADC achieves an ENOB of$11.2-11.7$bits with a reconfigurable bandwidth of 10–50 kHz at a supply voltage of 0.6–1 V. The prototype ADC was fabricated using 28-nm CMOS technology, occupying an active area of 0.0575 mm2.

With the increasing computational demands of the neural networks, many hardware accelerators for the neural networks have been proposed. Such existing neural network accelerators often focus on popular neural network types such as convolutional neural networks (CNNs) and recurrent neural networks (RNNs); however, not much attention has been paid to attention mechanisms, an emerging neural network primitive that enables neural networks to retrieve most relevant information from a knowledge-base, external memory, or past states. The attention mechanism is widely adopted by many state-of-the-art neural networks for computer vision, natural language processing, and machine translation, and accounts for a large portion of total execution time. We observe today's practice of implementing this mechanism using matrix-vector multiplication is suboptimal as the attention mechanism is semantically a content-based search where a large portion of computations ends up not being used. Based on this observation, we design and architect A3, which accelerates attention mechanisms in neural networks with algorithmic approximation and hardware specialization. Our proposed accelerator achieves multiple orders of magnitude improvement in energy efficiency (performance/watt) as well as substantial speedup over the state-of-the-art conventional hardware.

A novel self-capacitance transition sensing method is presented for low-power touch detection using a capacitive touch-screen. While maintaining a voltage level, an additional electric charge is additionally required when a touch-input is newly added; the amount of charge is used for detection. Accordingly, the proposed current mirroring voltage-level regulation (CM-VLR) circuit senses the transition of self-capacitance of the touch-screen and detects motions of the touch-object. Only one CM-VLR cell is used to scan the entire touch-screen. Thus low-power readout and high integrated-circuit area efficiency are achieved. Moreover, the proposed self-capacitance sensing method does not require an offset-calibration step through a charge-sharing-based voltage generation and the offset-coverage capacitor. Fabricated in a 180-nm CMOS process, and the CM-VLR cell occupies 0.12 mm2. At a 120-Hz report rate, the proposed analog front-end (AFE) detects touch-input at a 32-dB SNR while dissipating 2.1 mW.