Rajeshwari Pandey

dblp:23/10431 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2026
0000-0002-7539-7888ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021
YearPublicationVenuePosition
2026 On the design of efficient Schmitt trigger digital logic gates
Bhawanand Jha, Rajeshwari Pandey
Integr.3
2025 High-performance noise-tolerant DTMOS Domino Schmitt trigger logic gate design
Bhawanand Jha, Rajeshwari Pandey
Integr.2
2022 OTA Based Fractional-Order Oscillator With Controlled Phase Difference
abstract
In this manuscript, a new fractional-order (FO) oscillator is proposed, which employs two fractional-order capacitors (FOC) and two operational trans-conductance amplifiers (OTA). The difference of phase between two output voltages of FO oscillator can be independently controlled. Sensitivity of frequency of oscillations with respect to different circuit parameters is drafted mathematically. The functionality of the proposed structure is confirmed through SPICE simulations with 180nm CMOS technology model parameters and stability of the same is confirmed through pole plot in W-plane using forlocus function of MATLAB. Corner analysis and Monte-Carlo analysis are also carried out to illustrate the robustness of the proposed FO oscillator.
Garima Varshney, Neeta Pandey, Rajeshwari Pandey
ISCAS3