We investigate the effect of electrically induced thermal load on interconnect reliability and aging. We propose new models for uniform and non-uniform temperature evolution and its steady state distribution in interconnects considering Joule heating and heat convection. The models are verified by comparing the results against those of finite element experiments. We apply our models to study material migration induced aging and failures. We discuss how different non-uniform temperature profiles affect interconnect lifetime. We propose new formulas for accurate temperature aware assessment of the mortality of interconnects. We demonstrate that neglecting thermal effects in modern technologies may lead to incorrect conclusions about interconnect mortality. We also provide a method for modeling the true mean time to failure based on underlying physics.

In this paper, we study the main interconnect aging processes: electromigration, thermomigration and stress migration and propose comprehensive yet compact models for transient and steady states based on hydrostatic stress evolution. Our model can be expressed in terms of voltages only which abstracts away the hydrostatic stress. The model also explains some experimental observations, introduces temperature-dependent Blech's length criterion and a new time-to-failure formula replacing Black's empirical model. A tool is developed based on the proposed model which assesses reliability of multi-segment complex interconnect networks. Experimental results obtained on IBM benchmarks validate the model.

The majority of the existing experimental, theoretical and modeling works on electromigration (EM) are focused on simple, via-to-via structures, but complex interconnect structures have not been studied well. The lack of correct models for such interconnects may result in either conservative or weak design decisions which may result in catastrophic reliability failures. This paper proposes a physical model which holds for material migration as well as for lattice vacancy generation/annihilation. Using the developed model, well known circuit level EM assessment methods are examined by finite element modeling and simulation. The paper provides a compact model for EM analysis which can be easily implemented in CAD tools. We also explain some recent experimental results and empirical models published by other researchers.

This paper proposes integrating mutation analysis into model checking to improve coverage metrics of digital circuits. In contrast to traditional mutation testing where mutant faults are generated and injected into the code description of the model, we apply a series of newly defined mutation operators directly to the model properties rather than to the model code. We claim that any mutant properties that are generated from the initial properties and validated by the model checker should be considered as new properties that have been missed during the initial verification procedure. Therefore, adding these newly identified properties to the existing list of properties improves the coverage metric of the formal verification and consequently lead to a more reliable design. Preliminary simulation results of applying this approach to a 4x4 Booth-Multiplier with 6 and 8 initial properties, demonstrates a 40% and 45% coverage improvement respectively compared to the initial coverage metric.