We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant delay improvement is possible by this new approach.

In this paper we present a set cover based approach (SCP) to multi-way partitioning for minimum delay for Look-Up Table based FPGAs.SCP minimizes the number of chip-crossings on each circuit path with minimum logic duplication costs to achieve implementations with minimum delay and minimum number of chips.The overall complexity of SCP is (V 2 ).Experimental results demonstrate that SCP produces partitions that on the average have 14% fewer chips, 28% fewer pins, and 93% fewer chip-crossings on each circuit path compared to ANN which is a simulated annealing based implementation of classical multi-way partitioning.SCP achieves this performance and compact packing at the cost of duplicating 13% of logic on the average.Additionally, in comparison with a lower bound we observe that SCP has produced near-optimal solutions.

Article Performance directed technology mapping for look-up table based FPGAs Share on Authors: Prashant Sawkar View Profile , Donald Thomas View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 208–212https://doi.org/10.1145/157485.164672Published:01 July 1993 28citation199DownloadsMetricsTotal Citations28Total Downloads199Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access