Abstract Accuracy remains the dominant evaluation metric in Intrusion Detection System (IDS) research, yet an IDS that detects attacks too late is functionally equivalent to one that fails—particularly in Internet of Things (IoT) environments. In operational settings, the timing of detection shapes both the scope of adversarial activity and the feasibility of effective response. To the best of our knowledge, latency (the speed at which intrusions are identified) has received no systematic attention. Our analysis of published IDS papers reveals that latency is defined inconsistently—often referring to inference, communication, computation time, or combinations of these-leading to incomparable performance claims. To close this gap, we formally define end-to-end latency as the sum of three measurable components: Attacker-Controlled Latency (ACL), IDS-Determined Latency (IDL), and Post-Detection Latency (PDL). The framework further decomposes IDL into environment-specific sub-components, linking network topology and detection methodology to overall responsiveness. The framework provides a systematic mechanism to parameterize and vary these components across deployment environments (edge, cloud, federated learning). Using a Cyber-Physical dataset, we demonstrate the applicability of our latency framework to an existing dataset. By providing a mechanism to quantify detection timeliness, the proposed framework enables analysts to estimate attacker dwell time, benchmark real-time responsiveness, and standardize latency reporting across IDS studies.

Countermeasures and deterrents to power side-channel attacks targeting the alteration or scrambling of the power delivery network have been shown to be effective against local attacks where the malicious agent has physical access to the target system. However, remote attacks that capture the leaked information from within the IC power grid are shown herein to be nonetheless effective at uncovering the secret key in the presence of these countermeasures/deterrents. Theoretical studies and experimental analysis are carried out to define and quantify the impact of integrated voltage regulators, voltage noise injection, and integration of on-package decoupling capacitors for both remote and local attacks. An outcome yielded by the studies is that the use of an integrated voltage regulator as a countermeasure is effective for a local attack. However, remote attacks are still effective and hence break the integrated voltage regulator countermeasure. From the experimental analysis, it is observed that within the range of designs' practical values, the adoption of on-package decoupling capacitors provides only a 1.3x increase in the minimum number of traces required to discover the secret key. However, the injection of noise in the IC power delivery network yields a 37x increase in the minimum number of traces to discover. Thus, increasing the number of on-package decoupling capacitors or the impedance between locally measured power and the IC power grid should not be relied on as countermeasures to power side-channel attacks, for remote attack schemes. Noise injection should be considered as it is more effective at scrambling the leaked signal to eliminate sensitive identifying information.

A 3D architecture made up of a CMOS layer combined with a 3D stack of bipolar memristor crossbar arrays provides an innovative approach to hardware support for utilizing the strength of CMOS combined with the strength of memristors. Memristors have been evaluated for implementing a broad spectrum of applications such as memory, computations, hardware-based security primitives, cryptography, etc., and numerous studies have shown that memristors are desirable candidates for such applications. This paper proposes a novel 3D memristive crossbar architecture (i.e., a stack of memristive crossbar arrays built on top of CMOS substrate) with a specific focus on the way of connecting the crossbar arrays to the CMOS layer. The proposed architecture is configurable and allows restructuring crossbar arrays and creating 1D arrays with adjustable sizes. The proposed architecture enables parallel and pipeline computations where data can move or be processed in planes perpendicular to the stacked crossbar arrays. In addition, the proposed architecture is scalable meaning that stacks of crossbar arrays can be connected without additional overhead. This paper shows examples of implementing a full adder, a 4-bit look-ahead carry generator, and an 8-bit multiplexer. Simulations and area, delay, and power analysis demonstrate the behavior of the proposed 3D circuit.

Wireless sensor network (WSN) focuses on various properties such as, clustering, authentication, routing, security, reliability and resource usage. Among these security is a critical issue in hostile environments. In this paper, a cluster-based routing algorithm is performed through adaptive lightweight cryptographic scheme. Firstly, we form clusters using improved fuzzy C means (iFCM) clustering. Then we select the optimum and reliable path to send data using improved artificial bee colony (iABC) algorithm. To construct a path, we consider node degree, node residual energy, valid distance and node mobility. A lightweight encryption approach is concerned for secure data transmission using RC6 block cipher algorithm. Once the simulation tests evaluated on NS3.26 network simulator, the experimental results obtained showed for our proposed work and it achieves good performance in terms of memory usage, communication overhead, transmission delay, bit error rate, energy consumption, computation time for encryption and decryption and packet delivery ratio.

This paper describes a CMOS-memristive programmable logic device connected to CMOS XOR gates (mPLD-XOR) for realizing multioutput functions well suited for two-level {NAND, AND, NOR, OR}-XOR-based design. This structure is a generalized form of AND–XOR logic where any combination of NAND, AND, NOR, and OR, and literals can replace the and level. For mPLD-XOR, the computational delay, which is measured as the number of clock cycles, equals the maximum number of inputs to any output XOR gate of a function assuming that the number of XOR gates is large enough to calculate the outputs of the function simultaneously. The input levels of functions are implemented with novel programmable diode gates, which rely on the diode-like behavior of self-rectifying memristors, and the output levels of functions are realized with CMOS modulo-two counters. As an example, the circuit implementation of a 3-bit adder and a 3-bit multiplier are presented. The size and performance of the implemented circuits are estimated and compared with those of the equivalent circuits realized with stateful logic gates. Adding a feedback circuit to the mPLD-XOR allows the implementation of a multilevel XOR logic network with any combination of sums, products, XORs, and literals at the input of any XOR gate. The mPLD-XOR with feedback can reduce the size and number of computational steps (clock cycles) in realizing logic functions, which makes it well suited for use in communication and parallel computing systems where fast arithmetic operations are demanding.

Speaker recognition is one biometric used in identity authentication. As use of biometric systems become more widespread the need for robustness in various environments and applications becomes more significant. One such variable is recording equipment. Speaker recognition systems in distributed environments, such as the internet, are likely to use different microphones to perform identity authentication. The success rates for speaker recognition systems are dependent upon the variability of the recording system performance in a speaker recognition system. This paper investigates how speaker recognition false accept, false reject rates are affected by variations in recording systems.

I/sub DDQ/ testing is required for high quality products. Several barriers to I/sub DDQ/ testing have fallen. This is due to the rising importance of testing, quality, and CAD tool integration of design and test. Both theory and practice have demonstrated the value of I/sub DDQ/ testing methodologies. Three key issues still hinder widespread utilization of I/sub DDQ/. The first issue is how does I/sub DDQ/ compete with other test methods. The second issue is what measurement techniques can be used. And the third issue is how to set the I/sub DDQ/ current limit to catch defective parts without rejecting defect-free parts. The thesis of this presentation is that the issues are being actively worked, and the barriers will fall.

This paper presents an algorithm to route multiple nets for VLSI layout synthesis in the presence of irregular rectilinear obstacles. The proposed routing algorithms are to be used when layout is nearly finished. Any incremental routing for performance needs to be done by using the very limited space between existing layout cells or by routing directly over the cells. Each net has multiple pins, which are located either on the boundary or anywhere inside the layout region. The proposed algorithm is very systematic and easy to implement. It does not require any net sequencing, and through extensive experiments on real circuits has been shown to always produce near optimal solutions.>

An efficient algorithm for searching for functional cells based on Boolean matching in a large library is presented. Redundant variables and permutation of inputs are considered in this algorithm. The algorithm does a search in constant time, independent of the size of the library.>

New algorithms are proposed to route multiple points for VLSI layout synthesis in the presence of irregular rectilinear obstacles. The proposed routing algorithms are to be used when layout is nearly complete, such that routing needs to be done by using very limited space between existing layout cells or by routing directly over the cells. A point-to-point routing algorithm is proposed. Which allows more general conditions, including point-to-path routing, over-the-cell routing, multi-layer routing and user guided routing. Then, the point-to-point routing algorithm is generalized to perform multi-point routing. Through benchmarks, we have found that the results of the router either match or outperform those generated by existing algorithms, using significantly fewer search lines.>

The first behavioral synthesis scheme for improving testability in data path allocation independent of test strategy is presented. The authors propose two behavioral synthesis-for-test heuristics: improve observability and controllability of registers, and reduce sequential depth between registers. Also presented are algorithms that optimize a behavior-level design using these two criteria while minimizing area. Experimental results for benchmark circuits synthesized by the author's experimental system. PHITS, show that these methods give a high fault coverage in small amounts of CPU time at a low area overhead.>

It is shown that the traditional approach to diagnosing stuck-at faults with fault dictionaries generated for stuck-at faults is not appropriate for diagnosing CMOS bridging faults. A novel technique for using stuck-at-fault dictionaries to diagnose bridging faults is described. Teradyne's LASAR was used to simulate bridging and stuck-at faults in a number of combinational circuits, including parity trees, multiplexers, and the 74ASCI181 4-b, 16-function ALU (arithmetic and logic unit). When the traditional technique was used, between 30%-50% of the bridging faults were mis-diagnosed, with the presence of a failure indicated on a fault-free node. In addition, as the stuck-at-fault diagnostic ability of a test increased, the bridging fault diagnostic ability decreased. By use of the new technique. over 92% of the bridging faults in the circuits used for this research were diagnosed correctly and less than 4% led to misleading diagnoses.>