Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

H. M. Yassine

dblp:23/1691 · DBLP profile ↗
← Back
3ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 70% Processor architecture and microarchitecture · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.011997
A Signed-Digit Architecture for Residue to Binary Transformation · IEEE Trans. Computers 1997
Integrated circuit design
residue number system arithmetic		 0.011997
A Signed-Digit Architecture for Residue to Binary Transformation · IEEE Trans. Computers 1997
Processor architecture and microarchitecture › computer arithmetic
signed digit representation		 0.011997
A Signed-Digit Architecture for Residue to Binary Transformation · IEEE Trans. Computers 1997
Integrated circuit design › digital arithmetic circuits
redundant adders		 0.011997
A Signed-Digit Architecture for Residue to Binary Transformation · IEEE Trans. Computers 1997

Methods — techniques the papers use, named apart from their topics

signed-digit representation · 0.0end-around carry · 0.0chinese remainder theorem · 0.0
YearPublicationVenuePosition
1997 A Signed-Digit Architecture for Residue to Binary Transformation
abstract
A residue to binary converter architecture based on the Chinese Remainder Theorem (CRT) is presented. This is achieved by introducing a general moduli set S/sup k/ S/sup k/={2/sup m/-1, 2/sup 2om/+1, 2/sup 21m/+1, 2/sup 22m/+1,....,2/sup 22km/+1} for Residue Number System (RNS) applications. Residue to binary converter architectures based on moduli sets S/sup o/={2/sup m/-1, 2/sup m/+1} and S/sup 1/=(2/sup m/-1, 2/sup m/+1, 2/sup 2m/+1) are developed. The conversion procedure is performed in the following three levels: residue to signed-digit, signed-digit to binary, end-around carry addition/subtraction. In the first level of operation, the signed-digit representation of the CRT equation is realized by using redundant adder/subtracter blocks. Here, the necessary embedded multiplications are replaced by simple shift-left operations and the carry propagation is totally eliminated. In the second level, the redundant representation of CRT is directly converted to binary format. Finally, an end-around carry (EAC) addition/subtraction is performed to obtain the result at the third level of operation. The proposed architectures are simple, fast, free of memory blocks and module adders.
F. Pourbigharaz, H. M. Yassine
 IEEE Trans. Computers2
1994 Modulo-Free Architecture for Binary to Residue Transformation with respect to {2m-1, 2m, 2m+1} Moduli Set
abstract
A binary to residue converter architecture based on the.>
F. Pourbigharaz, H. M. Yassine
 ISCAS2
1994 Intermediate Signed-Digit Stage to Perform Residue to Binary Transformations Based on CRT
abstract
A residue to binary converter architecture based on the Chinese Remainder Theorem (CRT) is presented. The conversion from residue to binary is performed in three levels: residue to signed-digit; signed-digit to binary; end-around carry adder/subtracter. By choosing the residue number systems based on (2/sup m/-1, 2/sup m/+1) or (2/sup m/-1, 2/sup m/+1, 2/sup 2m/+1) moduli sets, the necessary multiplication operations embedded within the CRT can be replaced by simple shift left operations. The CRT equation is realized by using redundant adder/subtracter blocks in the first level and the carry propagation is totally eliminated. The second level of operation converts the redundant form of CRT to the binary representation. The proposed architecture is free of modulo-M adders. This is achieved by using an end-around carry propagate adder/subtracter in the third level. The two moduli converter was designed and simulated on Cadence.>
F. Pourbigharaz, H. M. Yassine
 ISCAS2