Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Jih-Ming Fu

dblp:23/2073 · DBLP profile ↗
← Back
4ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 75% Parallel and multicore computing · 25%
Software engineering, system software, and programming languages
1 paper
Program verification · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Program verification › system verification
embedded software verification
0.012004
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software · IEEE Trans. Software Eng. 2004
Program verification
model checking
0.012004
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software · IEEE Trans. Software Eng. 2004
Embedded and real-time systems
component-based design
0.012004
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software · IEEE Trans. Software Eng. 2004
Embedded and real-time systems › embedded software
embedded software design
0.012004
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software · IEEE Trans. Software Eng. 2004
Parallel and multicore computing › dataflow computing › dataflow scheduling
quasi-static scheduling
0.012004
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software · IEEE Trans. Software Eng. 2004
Embedded and real-time systems
real-time scheduling
0.012004
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software · IEEE Trans. Software Eng. 2004

Methods — techniques the papers use, named apart from their topics

model checking · 0.1UML · 0.1
YearPublicationVenuePosition
2007 Real-Time Embedded Software Design for Mobile and Ubiquitous Systems
Pao-Ann Hsiung, Shangwei Lin 0001, Chin-Chieh Hung, Jih-Ming Fu, Chao-Sheng Lin, Cheng-Chi Chiang, Kuo-Cheng Chiang, Chun-Hsien Lu, Pin-Hsien Lu
EUC4
2005 SESAG: an object-oriented application framework for real-time systems
abstract
Abstract Advancements in hardware and software technologies have made possible the design of real‐time systems and applications where stringent timing constraints are imposed on critical tasks. The design of such systems is more complex than that of temporally unrestricted systems because system correctness depends on the satisfaction of functional as well as temporal requirements. To aid users in correctly and efficiently designing systems, object‐oriented frameworks provide a useful environment for significant reuse and reduction in design effort. In contrast to other application domains, there has been relatively little work on an application framework for the design of real‐time systems. Facing the growing need for real‐time applications, we propose a novel application framework called SESAG, which consists of five components, namely Specifier, Extractor, Scheduler, Allocator, and Generator. Within SESAG, several design patterns are proposed and used for the development of real‐time applications. A new evaluation metric called relative design effort is proposed for evaluating SESAG. Experiences in using SESAG show a significant increase in design productivity through design reuse and a significant decrease in design time and effort. Two complex application examples have been developed using SESAG and evaluated using the new evaluation metric. The examples demonstrate relative design efforts of at most 18% of the design efforts required by conventional methods. Copyright © 2005 John Wiley & Sons, Ltd.
Pao-Ann Hsiung, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See
Softw. Pract. Exp.3
2004 VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software
abstract
The growing complexity of embedded real-time software requirements calls for the design of reusable software components, the synthesis and generation of software code, and the automatic guarantee of nonfunctional properties such as performance, time constraints, reliability, and security. Available application frameworks targeted at the automatic design of embedded real-time software are poor in integrating functional and nonfunctional requirements. To bridge this gap, we reveal the design flow and the internal architecture of a newly proposed framework called verifiable embedded real-time application framework (VERTAF), which integrates software component-based reuse, formal synthesis, and formal verification. A formal UML-based embedded real-time object model is proposed for component reuse. Formal synthesis employs quasistatic and quasidynamic scheduling with automatic generation of multilayer portable efficient code. Formal verification integrates a model checker kernel from SGM, by adapting it for embedded software. The proposed architecture for VERTAF is component-based and allows plug-and-play for the scheduler and the verifier. Using VERTAF to develop application examples significantly reduced design effort and illustrated how high-level reuse of software components combined with automatic synthesis and verification can increase design productivity.
Pao-Ann Hsiung, Shangwei Lin 0001, Chih-Hao Tseng, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See
IEEE Trans. Software Eng.5
2001 Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks
abstract
Producing correct software is a major goal for application frameworks that are targeted at embedded real-time systems because incorrect software is of no use and may also cause severe system damage. It is shown how formal verification can be elegantly, seamlessly, and scalably integrated into a component-based object-oriented application framework for embedded real-time systems. Two issues in such technology integration are addressed: (1) the choice of a common system model, and (2) the integration of formal synthesis and model checking. Solutions are provided, respectively, in the form of (1) proposing a new formal object-oriented model (FOOM), and (2) the execution of model checkers within synthesis algorithms. Technically, we propose a compositional software verification framework, in which model checking is employed, with state-space reduction techniques adapted for embedded real-time software. A separate verifier component is proposed for modular integration as illustrated by its implementation in the VERTAF application framework. An example illustrates the success of our approach and the benefits gained through integrating formal verification.
Pao-Ann Hsiung, Win-Bin See, Trong-Yen Lee, Jih-Ming Fu, Sao-Jie Chen
APSEC4