Partitioning memristive crossbar is emerging as a new technique for improving computational throughput, and overcoming trade-offs in memristive Processing-In-Memory (PIM) architecture. This paper presents a complete framework for realizing logic functions inside a partitioned memristive crossbar. This work utilizes a heuristic-based clustering algorithm on And-Inverter-Graphs (AIGs) to minimize the number of lookup tables (LUTs) necessary for mapping Boolean logic functions. In our proposed mapping technique, LUTs are evaluated using single-row Memristor Aided loGIC (MAGIC) based NOR gates, and mapped inside the partitioned memristive crossbar. The peripheral design for partitioned crossbar utilizes a shared CMOS decoder, and generates Opcodes to control logic computation across all partitions. The experimental results show an average throughput improvement of 12.58×, 68.47×, 156.10×, 107.76×, and 506.22× over SIMPLER, ReVAMP-ArC, ReVAMP-DeC, m-AIG based mapping technique, and CoMIC-3D mapping, respectively. In addition, on average, a 47.4% reduction in computation area is observed.

With the emergence of all-inclusive AI/ML applications, hardware solutions, commonly known as AI-Accelerators (AIA), are now being widely adopted to emulate deep neural networks (DNN) to facilitate faster and large-scale data analytics. An AIA-chip comprises a 2D systolic array of identical processing units (PEs), registers, and glue logic. These arrays may be implemented with traditional digital logic or with analog primitives such as memristors. As the packing density of AIA-chips increases, they become vulnerable to various manufacturing defects thereby compromising yield and the accuracy of prediction. In this review article, we summarize various methods that have been recently proposed for expediting Automatic Test-Pattern Generation (ATPG) for stuck-at and transition faults in AIA-arrays. Other relevant issues such as fault-criticality, self-test, fault-recovery, and the asymmetry of fault behavior, are also discussed.

The field of integrated circuits has undergone re-markable changes over the past decades. With the increasing demand for performance constraints and the ever-reducing size of the Integrated circuits chips, analog and mixed-signal designs have become indispensable and increasingly complex in modern CMOS technologies. The traditional method for testing analog circuits, which is still commonly used in the industry today, makes sure that the circuits comply with all of the specifications set forth in the data sheet. But a specification-based testing technique suffers from high test costs brought on by prolonged testing on pricey test equipment. The situation has only become worse in recent years to the point where analog circuit test costs are frequently reported to be as much as 50 % of the total test costs despite analog components taking up less than 5% of the chip size. In this work, both fault detection and diagnosis techniques have been presented via statistical and machine learning by processing the output response of the corresponding faulty circuit in a non-conventional domain (i.e., statistical and time-frequency domain).

Recent advances of microelectrode-dot-array (MEDA) based Biochips have revolutionized the application of Lab-on-chip devices. New techniques for MEDA based biochips confide on the concepts on computer-aided design automation and cyberphysical integration to provide ease of use, higher throughput and reliability. One of the major security concerns in MEDA based biochips is actuation tempering attacks targeted to change control sequence daisy chain input resulting in incorrect bioassays. In this paper, we attempted to identify different types of actuation tampering attacks specific to MEDA based biochips. We proposed one technique to detect errors in order to secure the biochips against actuation tempering attacks. This proposed technique is able to monitor such malicious operations and can stall it under any abnormality in operation. Our analysis proves that the proposed method is able to detect errors accurately and proves that this technique is naturally implemented in MEDA.

Recent advances in microfluidics and microfabrication technology enabled the emergence of a new microelectrode-dot-array (MEDA) architecture for microfluidic biochips. The MEDA-based design allows dynamic routing with variable-sized droplets. The cross contamination avoidance between droplets of different biomolecules subjected for analysis and detection on MEDA architecture poses a major design challenge for development of MEDA-based biochips. In this article, we propose a precise technique for droplet routing with minimal cross contamination for MEDA-based biochips. Here we first evaluate the probability of cross contamination between any two droplets within the 2-D MEDA layout. Thereby, we propose a routing scheme for functional droplets specifically targeted for intelligent cross-contamination avoidance. As evident from the experimental results, the proposed technique effectively reduces both intra and inter subproblem cross contaminations. Experiment results shows considerable improvements over contemporary works.

Features extracted from single domain information cannot maximally reveal the state of the circuit since parametric fault features of analog circuits are quantified according to the application of the circuit. To combat this shortcoming, features from time, frequency, wavelet and statistical domain have been fused to construct ultimate fault features of the circuit. Data fusion has been performed in two steps, data whitening and Principal component analysis (PCA). The fused features are used to train SVM classifier for fault diagnosis of analog circuits. The proposed method is illustrated with the example of Sallen-Key band pass filter circuit and four OpAmp biquad high pass filter circuit. The accuracy of fault classification of the proposed method with fused features is found considerably higher than that with individual domain features.

Convolutional Neural Network (CNN) is the state-of-the-art learning technique for image understanding in several artificial vision systems. Extensive uses of memory storage and bandwidth with high computation capacity boost up the performance of a CNN. Convolution is the fundamental operation in CNN models and hence a large number of multiplier-accumulator (MAC) unit is required to compute the convolution operations adequately. MAC processing incurs extreme computational complexity by consuming significant amounts of time, energy and area. These limitations in computation have led to the exploration of different architecture of MAC to meet the demand of CNN processing. To increase the overall speed of a CNN model, an architecture called SAC (shift-accumulator) is proposed that reduces the number of overall convolution computations. Further, the SAC architecture is especially designed for convolution operations used in image sharpening, edge detection, blurring etc. The proposed SAC architecture facilitates faster convolution computations and reduces the overhead in terms of area and power than the conventional MAC architecture. Although the accuracy is slightly reduced, it does not significantly affect the efficacy of computational unit used in CNN processing.

Recent advancement of microelectrode-dot-array (MEDA)-based architecture for digital microfluidic biochips has enabled a major enhancement in microfluidic operations for traditional lab-on-chip devices. One critical issue for MEDA-based biochips is the transportation of droplets. MEDA allows dynamic routing for droplets of different size. In this article, we propose a high-performance droplet routing technique for MEDA-based digital microfluidic biochips. First, we propose the basic concept of droplet movement strategy in MEDA-based design together with a definition of strictly shielded zones within the layout in MEDA architecture. Next, we propose transportation schemes of droplets for MEDA architecture under different blockage or crossover conditions and estimate route distances for each net in offline. Finally, a priority-based routing strategy combining various transportation schemes stated earlier has been proposed. Concurrent movement of each droplet is scheduled in a time-multiplexed manner. This poses critical challenges for parallel routing of individual droplets with optimal sharing of cells formulating a routing problem with higher complexity. The final compaction solution satisfies the timing constraint and improves fault tolerance. Simulations are carried out on standard benchmark circuits, namely, Benchmark suite I and Benchmark suite III. Experimental results show satisfactory improvements and prove a high degree of robustness for our proposed algorithm.

Microfluidic chips are now being increasingly used for fast and cost-effective implementation of biochemical protocols. Sample preparation involves dilution and mixing of fluids in certain ratios, which are needed for most of the protocols. On a digital microfluidic biochip (DMFB), these tasks are usually automated as a sequence of droplet mix-split steps. In the most widely used (1:1) mix-split operation for DMFBs, two equal-volume droplets are mixed followed by a split operation, which, ideally, should produce two daughter-droplets of equal volume (balanced splitting). However, because of uncertain variabilities in fluidic operations, the outcome of droplet-split operations often becomes erroneous, i.e., they may cause unbalanced splitting. As a result, the concentration factor (CF) of each constituent fluid in the mixture may become erroneous during sample preparation. All traditional approaches aimed to recover from such errors deploy on-chip sensors to detect possible volumetric imbalance, and adopt either checkpointing-based rollback or roll-forward techniques. Most of them suffer from significant overhead in terms of assay-completion time, reactant-cost, and uncertainties in termination due to randomly occurring split-errors. In this paper, we propose a new approach to accurate dilution preparation on a DMFB that is oblivious to volumetric split-errors. It does not need any sensor and can handle multiple split-errors, deterministically. The proposed method is customized for each target-CF based on the criticality of split-errors in each mix-split step. Simulation experiments on various test-cases demonstrate the effectiveness of the proposed method.

Digital microfluidic biochip has been developed as a promising alternative to the traditional approach of benchtop biochemical laboratory tests. Dependability is an important attribute for microfluidic biochips that are used for safety-critical applications, such as point-of-care health assessment, air-quality monitoring, and food-safety testing. Therefore, the robust offline and online test techniques are required after manufacturing and during bioassay operations. In this work, we are presenting an image segmentation based testing methodology to detect the catastrophic faults and to locate the faulty cells. The design-for diagnosability scheme is proposed, and it is shown that faults can be located and tolerated by providing alternative paths in biochips. Moreover this testing method also facilitates the testing of a biochip with other bioassay operations running concurrently.

Three-dimensional Integrated Circuit (3D IC) based on through silicon via (TSV) has brought a drastic change in the IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for the system operation. So, testing of TSV is essential for 3D IC. In this paper a cost-effective Built-in Self-Test (BIST) mechanism is proposed for the post-bond test of TSVs in 3D ICs. The test method aims at identifying single and multiple defective TSVs using low test time with minimum hardware. The time cycle needed for testing is calculated and is compared with previous proposed methods. The simulation result shows that the proposed BIST circuit is beneficial over prior BIST technology in terms of test time cycle and hardware requirement.

A statistical approach is proposed to detect parametric fault in linear and weakly non-linear analog circuits by mapping faults to a statistical metric, Bhattacharyya distance which is measured from the Probability Density Function (PDF) of the outputs. The non-Gaussian Auto-regressive (AR) model is used to estimate the PDF. To validate the proposed statistical approach, we have simulated two benchmark circuits, Sallenkey band pass filter and cascade amplifier with CADENCE Virtuoso using umc-180nm technology. Defect screening is also measured with linear regression analysis. Detectability of the proposed method for parametric fault is reasonably large compared to the functional test method.

In this article, we introduce a novel method of synthesizing symmetric Boolean functions with reversible logic gates. In contrast to earlier approaches, the proposed technique deploys a simple, regular, and cascaded structure consisting of an array of Peres and CNOT gates, which results in significant reduction with respect to the quantum cost. However, the number of circuit inputs may increase slightly when such cascades are used. In order to reduce their number, we next propose a postsynthesis optimization phase that allows judicious reuse of circuit lines. In addition to offering a cost-effective synthesis methodology, the proposed reversible logic structure supports elegant testability properties. With respect to all single or partial missing gate faults (SMGFs and PMGFs), or repeated gate faults (RGFs) in such an n -input circuit module, we show that it admits a universal test set of constant cardinality (=3) for any value of n . Thus, considering both the cost and testability issues, this approach provides a superior option for synthesizing symmetric functions compared to existing designs.

Present-day focus on multicore research has not only increased computing power but also power- and bandwidth-efficient communication among cores. On-chip communication networks have become popular today because of their low energy use and modular structure compared to bus-based interconnects. Silicon photonics has further boosted the performance of on-chip interconnection networks with its low energy-delay product and high reliability. In current multicore Network-on-Chip (NoC) architectures, photonics is playing an important role in transferring large volumes of data both on- and off-chip. The problem addressed in this work is the issue of broadcast traffic arising due to invalidation requests from on-chip cache memories. Although such traffic is typically less than 1% of total traffic, it can easily present a high load on network resources, creating congestion and degrading performance. In this article, we propose a CDMA-based, secure, scalable, and energy-efficient technique to eliminate broadcast invalidations and increase overall performance. Experimental results indicate a performance boost up to 22.2% over a competing Photonic NoC and up to 57.4% over Electrical Mesh-based NoC when the proposed technique is used. Additional hardware deployed has an area overhead of less than 1%, whereas total energy consumed is at par with other state-of-the-art techniques.

Digital microfluidic biochips (DMFBs), a second-generation lab-on-chip device has developed in recent years as a feasible alternative to conventional laboratory procedure for biochemical analysis and diagnostic applications. These devices enable the precise manipulation of nanoliter volumes of biological fluids and chemical reagents within a 2-D rectangular array of electrodes. Increasing number of control pin requirements together with high wire planning complexity becomes a major issue for integrated execution of multiple bioassays within a single DMFB layout. In this paper, we propose new techniques for interconnection wire routing for actuating the electrodes operating at identical time sequence. Here, we propose three different algorithms to develop feasible wire plans for a given layout with an aim to minimize the overall number of control pin count. Multiple actuation on the same pin termed multiphasing is proposed to resolve the issue of wire planning for handling the issue of cross contamination at any particular site. The proposed techniques are implemented in layouts using testbenches for benchmark suite III and selective testbenches for benchmark suite I. The results obtained through simulation show encouraging improvement over contemporary contributions.

Quantum reversible circuit is a new emerging technology attracting the researchers. A reversible circuit is composed of reversible gates only. A reversible Toffoli gate has two components - the control and the target. The missing gate fault model is used for modelling defects in quantum k-CNOT gate. This work introduces Boolean Difference technique for deriving the test set for detecting all faults in a reversible circuit implemented with k-CNOT gates. Then a optimizing algorithm is used to derive optimal test set to detect all possible partial missing faults in a circuit.

3D integrated circuit (3D IC) is becoming challenging for increasing power density and design complexity. Due to vertical integration heat dissipation in 3D IC is increased that creates hotspots on chip and hence temperature of the chip is very serious issue. Traditional fan-based cooling technique is insufficient for 3D ICs. Hence inter-die integrated microchannel cooling technique and dummy thermal Through-Silicon-Vias (TSVs) based techniques are used for controlling thermal behaviour of the chip. In this paper, we have proposed two temperature estimation models for 3D IC based on liquid cooled microchannels and thermal TSVs. Experimental results show that thermal simulation using our approach provide same result compared to [1]. For microfluidic cooling, our proposed thermal simulator is much more accurate than proposed model [2] and less than 0.5% error respect to simulation result with COMSOL thermal simulator using the same experimental environment of [2].

Recent works in the synthesis of reversible logic circuits have been motivated by ever increasing emphasis on low-power design alternatives, and recent developments in quantum computing. Although most of the synthesis approaches use multiple-control Toffoli (MCT) gates with positive control lines, a few recent works have also considered MCT gates with negative control lines resulting in better circuit realizations. Some of the works have also tried to carry out post-synthesis optimization of given MCT gate netlists with positive control lines, using template matching and similar netlist transformation techniques. However, only one work is reported that attempts to optimize netlists containing negative control MCT gates. This paper proposes an efficient optimization technique for MCT gate netlists with both positive and negative control lines, which is based on repeated applications of a small set of pairwise gate merging and replacement rules. Experiments carried out on reversible circuit benchmarks show that it is possible to achieve significant reductions in number of gates and quantum costs.

A digital microfluidic biochip (DMB) is often deployed for multiplexing several assays in space and in time. The residue left by one assay may contaminate the droplets used for subsequent assays. Biochemical assays involving cell culture and those based on particle microfluidics also require sweeping of residual media from an active droplet on-chip. Thus, fluidic operations such as washing or residue removal need to be performed routinely either to clean contamination from the droplet pathways or to rinse off certain droplets on the chip. In this work, several graph-based techniques are presented for offline washing of biochips that may have either a regular geometry (e.g., a 2D array of electrodes), or an irregular geometry (e.g., an application-specific layout). The schemes can be used for total washing, that is, for cleaning the entire biochip or for selective washing of sites or pathways located sparsely on the chip. The problem of reducing the path length and washing time of the droplets is investigated with or without capacity constraints. The proposed algorithms for offline washing make use of several techniques such as graph traversal, integer linear programming (ILP) modeling, and customized heuristics based on the nature of the geometric distribution of the contamination profile. The contaminated pathways are assumed to be Manhattan or curved, and hence the techniques are applicable to the conventional field-actuated DMBs as well as to the emerging classes of light-actuated and active-matrix DMBs. These techniques will be useful in enhancing the reliability of a wide class of emerging digital microfluidic healthcare devices

Reversible logic synthesis has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate faults (MMGF), are likely to be more suitable for modeling defects in quantum k-CNOT gates. This work proposes an algorithm for deriving the test set for the detection of all single missing gate faults in a reversible circuit implemented with k-CNOT gates. Instead of deriving test set directly for the detection of missing gate faults, a Boolean generator is developed by Boolean difference method to derive the test set and to detect all the single missing gate faults of a reversible circuit. Experimental results on some benchmark circuits are also reported.

Digital microfluidic biochips in recent years have been developed as a major alternative platform for conventional benchtop laboratory procedures. It offers better precision, scalability, higher sensitivity, lower cost due to smaller sample and reagent volumes. Testing of DMFBs is of major significance in terms of dependability and reliability issues for safety-critical applications. A series of complex microfluidic operations are executed in a compact 2D array within a DMFB. The layout engages a group of cells as transportation path as well as a specific cluster of cells as functional modules to perform basic operations of routing, mixing, splitting, merging, storage and detection. In order to determine the correctness and reliability of results testing of these prescheduled layout are necessary both for transportation (structural) as well as functionality (functional). In this paper we propose a technique for customized testing of a prescheduled layout within a microfluidic array. The test performs both structural as well as functional testing for specified cells that forms the layout. The simulations are carried out in testbenches of benchmark suite III and the results are compared with contemporary methods.

Synthesis of reversible circuits has attracted the attention of many researchers. In particular, approaches based on Decision Diagrams (DDs) have been shown beneficial since they enable the realization of corresponding circuits for large functions. However, all existing approaches rely on a gate library composed of positive control lines only. Recently, it has been shown that the additional use of negative control lines enables significant reductions of the respective circuit costs. In this paper, we aim for exploiting this potential. To this end, two complementary schemes are investigated. First, a post-synthesis optimization that exploits the power of negative control lines is utilized to optimize the circuits generated by previously proposed DD-based methods. Second, negative control lines are explicitly considered during synthesis. Experimental results demonstrate that the proposed approaches result in a significant reduction with respect to gate count as well as quantum costs.

Digital Microfluidic Biochips (DMFB), a promising platform for Lab-on-chip systems are capable of automated biochemical analysis targeted for medical diagnostics and other biochemical applications. The inherent nature of reconfigurability and scalability enables the device to integrate multiple bioassay protocols within the same array for simultaneous execution. Each execution of Bioassay involves numerous microfluidic operations to be performed successfully within the DMFB. Optical Detection and analysis are one of the significant operations required to be performed in DMFB systems for conclusive diagnosis and testing of targeted parameters within the specified sample. In this paper we propose a new design for automated detection based analyzer system integrated with a multipartioned scalable DMFB for two stage confirmatory detection of multiple parameters for a given set of samples .Multiple bioassays are executed sequentially in two stages and the results are analyzed using an intelligent system with integrated memory containing precharacterized standard outputs. The design prototype is implemented on FPGA platform and the simulations and detection results for a set of specified bioassay protocols are found to be satisfactory and in conformance with conventional benchtop laboratory processes.

Crosstalk effects in Multilayer Graphene Nano Ribbon interconnects (GNRs) are investigated with the help of ABCD parameter matrix approach for intermediate and global level interconnects at 11 nm technology node. For long intermediate and global levels of interconnects, the worst case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are far lesser than that of copper interconnects. Though neutral GNR interconnects introduce lesser worst case peak crosstalk noise voltage, it contributes more noise than its doped counterpart. Perfectly specular, doped multilayer zigzag GNR interconnects prove to be a suitable alternative to copper interconnects for future Integrated circuit.

The problem of reversible logic synthesis has drawn the attention of many researchers over the last two decades with growing emphasis on low-power design. Among the various synthesis approaches that have been reported, the ones based on compact circuit representations like Binary Decision Diagrams (BDD) and Exclusive-or Sum-Of-Products (ESOP) are interesting in the sense that they can handle large circuits with more than 100 inputs. The drawback of these approaches, however, is that the generated netlists are sub-optimal, and there is lot of scope for optimizing them. One of the best methods in this regard is an approach, where the ESOP cubes are grouped into sublists based on sharing among more than one outputs. In the work reported in this article, in contrast, an approach based on clustering the ESOP cubes based on their similarity with respect to input variables is presented, along with a technique to map each of the clusters into reversible gate netlists. This approach results in a significant reduction in quantum cost of the final netlist, but requires one additional garbage line. Experimental results on a number of reversible circuit benchmarks have been presented in support of the claim and also demonstrate that the method is very fast.

In this paper, we introduce a new method to realize symmetric Boolean functions with reversible logic based on unate decomposition. In contrast to earlier synthesis methods, our solution uses a simpler circuit structure of reversible gates, which enables a significant reduction with respect to quantum cost. The resulting design offers an improved solution to reversible synthesis of symmetric Boolean functions.

A second generation Lab-on-chip device termed as digital micro fluidic biochip (DMFB) has been developed in recent years as a time multiplexed reconfigurable device capable of executing multiple bioassay protocols simultaneously on a single 2D planar array. Optical detection, processing and analysis are considered to be of major significance in bioassay operations as this may influence the conclusive decisions involving diagnosis, detection and testing. Detection results obtained from a series of tests in a single biochip - may prompt to perform next sequence of tests on separate biochips in order to converge towards specific disease profile, diagnosis and determination of the future course of treatment. In this paper we have first proposed a design of a digital detection analyzer circuit to be coupled with a biochip for execution of prescheduled multiple bioassay protocols. The analyzer enables automated detailed analysis of the optical detection results based on the data acquired at the detection site through successful Biochip operation for heterogeneous droplet samples. we further proposed a design of centralized controller that operates on the basis of the digitized output pattern obtained from the proposed analyzer for a specific test sequence and logically determines the address of the next biochip to perform the next test sequences destined in the diagnostic process flow using an intelligent database stored in the integrated system memory. The synthesis, simulation for the overall system has been carried out using precharacterized reference data for measurement of different parameters of human blood samples and corresponding final detection results are displayed and verified successfully.

Digital microfluidic technology is being increasingly used for implementing a lab-on-a-chip with many life-critical applications. Testing of these biochips is thus indispensable not only after manufacture, but also during in-field operation. To keep the product cost (including both design and test) low for disposable biochips, efficient on-line test techniques are desirable. All previous on-line test mechanisms interleave testing and the target bioassay protocol, but they involve overhead such as use of separate test droplet(s) and increased completion time. In this paper, we propose a simple on-line error-detection methodology that can be performed concurrently with the normal operation of the system with no or little extra effort. The proposed procedure does not require any test droplet. In the case of incorrect operation, the error is detected on or before the completion of the bioassay. The main objective of the proposed strategy is to ensure the correctness of the executed assay on-chip and not to guarantee the absence of a defect in the chip. The given assay protocol is assumed to be executed correctly if the on-line procedure finishes with success. The assay is aborted as soon as an error is detected, thereby saving costly sample/reagents. Moreover, the scheme can be easily adopted to enhance diagnosis.

Digital Micro fluidic biochips have been developed as a promising platform for Lab-on-chip systems that manipulate individual droplet of chemicals on a 2D planar array of electrodes. Due to the significance of the correctness of the results -- fault tolerance and dependability becomes a major issue for operation of these devices. Therefore, such devices are required to be tested frequently both off-line (e.g., post manufacturing) and concurrently ahead of each assay execution. Under both scenarios, testing is accomplished by routing one or more test droplets across the chip simultaneously and recording their arrival at the destination. In this paper we attempted to solve the problem of customized testing for a given Bioassay layout. We have applied a look ahead strategy for parallel testing using multiple droplets for any given test bench with an objective of minimization of test completion time and optimized utilization of test resources. The test simulations are carried out on test benches of Benchmark suite III and results obtained are found to be encouraging.

Multiplexing several assays in time on the same digital microfluidic biochip is often needed in several biochemical applications. Contamination may lead to undesirable mixing of the residue left by one assay with the droplets of the subsequent assay. Hence, cleaning the droplet pathways of such a biochip by wash droplets between successive assays is required. Since a wash droplet may have a finite capability of residue removal, one has to design an efficient route planning for wash droplet(s) that minimizes the washing time and/or electrode actuation. In this paper, we formulate the problem in terms of graph Eulerization and Capacitated Chinese Postman Problem. We also propose efficient solutions and report some simulation results.

The use of microfluidics for building biochips is an emerging research area. A key challenge in this area is the droplet routing problem in the design of digital microfluidic biochips. It involves the scheduling of movement of a number of droplets in a time-multiplexed manner to avoid their cross-contamination. This paper attempts to solve this problem for multiple source and target locations with the objectives of minimizing (i) electrode usage, and (ii) latest arrival times. Hierarchical and preferential heuristic algorithms are proposed, and experimental results are observed to be quite encouraging.

Logic synthesis of reversible circuits has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. This article presents an efficient algorithm to derive an optimal test set (OTS) for detection of multiple missing-gate faults in a reversible circuit implemented with k-CNOT gates. It is shown that the OTS is sufficient to detect all single missing-gate faults (SMGFs) and all detectable repeated gate faults (RGFs). Experimental results on some benchmark circuits are also reported.

Digital micro fluidic technology is now being extensively used for implementing a lab-on-a-chip. Micro fluidic biochips are often used for safety-critical applications, clinical diagnosis, and for genome analysis. Thus, devising effective and faster testing methodologies to warrant correct operations of these devices after manufacture and during bioassay operations, is very much needed. In this paper, we propose a technique to obtain the route plan of a test droplet for the purpose of structural testing of biochips. The technique is applicable to fully reconfigurable arrays and application specific biochips. We propose an improved eulerization technique to implement the test plan based on a graph model of the chip. The optimal eulerization can be abstracted in terms of the classical Chinese postman problem. The Euler tour can then be identified using a cycle decomposition method, which is easy to implement. This can also be used in phase-based test planning leading to significant savings in testing time. The method provides a unified approach towards unidirectional structural testing and can be easily adapted to design an improved droplet routing procedure for bidirectional functional testing of digital micro fluidic biochips.

This paper presents an unified digit-serial systolic multiplication architecture for all-one polynomials (AOP) and trinomial over GF (2m) for efficient implementation of Montgomery Multiplication (MM) algorithm suitable for cryptosystem. This is the first reported unified digit serial systolic digit level pipelined MM architecture for AOP and trinomials over GF (2). Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less compared to earlier design for same class of polynomials. The proposed multiplier has clock cycle latency of (2N) where N=⌈m/L⌉, m is the word size and L is the digit size.

One of the recent areas of research interest is the use of microfluidics for building up biochips, the digital microfluidic biochips (DMFB). This paper deals with a challenging problem related to the design of DMFB. Specifically the design problem considered is related to high performance droplet routing, where each droplet has single source location and single target location. The objectives are (i) minimizing the number of electrodes used in the DMFB, and (ii) minimizing the total routing time of all the droplets or arrival time of a droplet that is the last to arrive at its target(latest arrival time). We propose a simple algorithm for concurrent path allocation to multiple droplets, based on the Soukup's routing algorithm [22], together with the use of stalling, and possible detouring of droplets in cases of contentions. Selection of the droplets is based on their respective source to target Manhattan paths. The empirical results are quite encouraging.

The wireless sensor network (WSN) encounters resource restrictions such as low computational power, reduced bandwidth & limited power resource and it demands efficient management of such resources. This work proposes a scheme (SSMCA), developed around the cellular automata (CA), for efficient management of battery power in sensor nodes with optimized cost of implementation. Each sensor node is assumed to be equipped with a segment of the CA, selected for the network that defines the state (active/standby) of the node at next time instant. The CA based management of status (active/standby) of a node ensures the reduced battery power consumption in nodes of a cluster as well as in the whole sensor network. As a segment of the CA is planted within a node, the additional cost for implementation of the proposed scheme is marginal. The simulation results establish that the SSMCA can better utilize the resources and ensure a maximally covered energy efficient sensor network.

Concurrent error detection and correction is an effective way to mitigate fault attacks in cryptographic hardware. Recent work on differential power analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energy consumed by a working digital circuit, it is possible to gain valuable information about the encryption algorithms used and even the specific encryption keys. Thwarting such attacks requires a new approach to logic and physical designs. This paper presents a systematic approach to fault tolerant cryptographic hardware designs. Firstly, the effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance variation of stream cipher algorithms with error detection and correction was studied by synthesising the designs on Field Programmable Logic Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Further, we analyse hardware building blocks to minimise switching activity of a circuit over all possible inputs and input transitions by adding redundant gates and increasing the overall number of signal transitions. We also discuss the overhead and compositional properties of uniformly-switching circuits.

In this paper, a scalable VLSI multiplication architecture based on Montgomery multiplication (MM) algorithm for elliptic curve cryptography (ECC) over GF(pm), where p is a positive prime and m is the degree of extension of the base field GF(p), is presented. The elements of the GF(pm) are in polynomial basis (PB) representation. The coefficients of the polynomials are represented in Montgomery residue format to simplify the multiplications over GF(p). The proposed algorithm of MM over GF(pm) requires m(m+1) MMs and m2additions over GF(p). However, the proposed architecture takes {m(m+1)Nmm+Nadd+1} cycles to compute MM over GF(pm), where Nmm> Nadd= 2, and Nmmand Naddare the numbers of cycles to complete an MM and an addition over GF(p), respectively. The security of an ECC scheme depends on the number of elements in GF(pm). Hence, for a p with nominal bit length (p≫2), the value of m can be small, but the GF(pm) still contains almost equal number of elements to a GF(2k), where k is positive integer. The complexity of the MM architecture over GF(p) is reduced by using carry-save-adder (CSA) based implementation, where NPEis the depth of the CSA. Analysis shows that the area complexity of the proposed architecture is significantly less. Implementation in AMS-0.35um technology, with L=30 (for p=536872717), m=23 and NPE=8, yields a clock frequency of 20.885 MHz, throughput of 6243.68 multiplications per second and power consumption of 86.8 mW (at 20 MHz).

It has been recently shown that observability of design for testability techniques compromises cryptographic hardware implementation security in a straightforward manner. During test, the chip can be configured so that it is possible to observe temporal data resulting from the encryption process of a plaintext that eventually exposes the secret key. To this end, we propose a C-testable S-box implementation which is one of the most complex blocks in advanced encryption standard hardware implementation. We divide the S-box structure into a positive polarity Reed–Muller form and tested independently using a BIST circuit. The proposed structure does not use any scan chain for testability, hence avoiding the vulnerability of the chip during testing. Only 14 constant vectors are sufficient to achieve 100% fault coverage in the S-box. The C-testable feature comes with an extra hardware overhead of 15 per cent. By introducing an on-chip testing feature one can avoid potential paths for introducing unwanted access into the on-chip security blocks.

This paper presents a test generation technique for detecting stuck-at(SAF)and transition delay fault(TDF)at gate level in the finite-field systolic multiplier over GF(2m) based on polynomial basis. The proposed technique derives test vectors from the cell expressions of systolic multipliers without any requirement of Automatic test Pattern Generation (ATPG) tool. The complete systolic architecture is C-testable for SAF andTDFwith only six constant tests. The test vectors are independent of the multiplier size. The test set provides 100% single SAF and TDF coverage.

Montgomery Algorithm for modular multiplication with a large modulus has been widely used in public key cryptosystems for secured data communication. This paper presents a digit-serial systolic multiplication architecture for all-one polynomials (AOP) over GF(2m) for efficient implementation of Montgomery Multiplication (MM) Algorithm suitable for cryptosystem. Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less than those of earlier designs for same classes of polynomials. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The proposed multipliers have clock cycle latency of (2N - 1), where N = ¿m/L¿, m is the word size andLis the digit size. No digit serial systolic architecture based on MM algorithm over GF(2m) is reported before. The architecture is also compared to two well known digit serial systolic architectures.

We propose a C-testable S-box implementation which is one of the most complex blocks in AES hardware implementation. Only 12 constant vectors are sufficient to achieve 100% fault coverage in the S-box. C-testability is achieved with an extra hardware overhead of 8.2 percent.

Structural testing of digital microfluidic biochips targets the detection of physical defects, but it does not guarantee robust execution of target bioassays or the integrity of assay outcomes. Functional testing is needed to detect fluidic malfunctions. Such tests ensure whether or not, the elementary fluidic operations, such as droplet transportation, mixing, incubation, and splitting are reliably executed on the microfluidic array. Routing test and mixing/splitting test are two important steps in functional testing. We present two procedures for optimal bidirectional routing test and accelerated mixing/splitting test. Compared to previous methods, these procedures need significantly fewer droplet manipulation steps and reduced execution time. The proposed method of functional testing in an N x N microfluidic array requires only a constant number of mixing/splitting steps. Further, the test outcome is free from boundary errors related to droplet size that may arise during mixing/splitting test.

In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order to detect the fault, the fault has high ingredient of delay dependent properties due to variation of the feedback path delay. Xilinx Jbits 3.0 API (Application Program Interface) is used to implement the BISTER structure in the FPGA. By using Jbits, we can reconfigure dynamically the device, in which the partial bit stream only affects part of the device. In the comparison to the traditional FPGA development tool (ISE), Jbits is faster to map the specific portion of the circuit to a specific tile. We also have more controllability over the utilization of internal resources of FPGA, so that we can perform this partial reconfiguration.

This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial-basis (PB) bit-parallel (BP) multiplier circuits over GF(2m). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of the ATPG tool. This low- complexity testing method requires (2m + 1) test vectors for detecting single stuck-at faults in the AND part and multiple stuck-at faults in the EXOR part of the multiplier circuits. The test vectors are independent of the multiplier's structure, as proposed in (T. A. Gulliver et al., 1991), but are dependent on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100 percent single stuck-at fault coverage.

We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2 m ) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys® tools using UMC 0.18 micron CMOS technology library.

Testing of bridging faults in a reversible circuit is investigated in this paper. The intra-level single bridging fault model is considered here, i.e. any single pair of lines, both lying at the same level of the circuit, may be assumed to have been logically shorted in order to model a defect. For an (n · n) reversible circuit with d levels realized with simple Toffoli gates, the time complexity of the test generation procedure is O(nd2 log2n). A test set of cardinality O(d log2n) is found to be sufficient for testing all such detectable faults. A minimal test set can also be easily derived by using the concept of test equivalence.

We present a C-testable method for detecting stuck-at (s-a) faults in the polynomial basis (PB) bit parallel multiplier circuits over GF(2m). It requires only 7 tests for detecting faults to provide 100% fault coverage, which is independent of the multiplier size. These 7 tests can be derived directly without any requirement of ATPG tools. Synopsysreg tool is used to generate ATPG based test patterns.

This paper presents a C-testable technique for detecting transition faults with 100% fault coverage in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m). The proposed technique requires only 10 vectors, which is independent of multiplier size, at the cost of 6% (avg.) extra hardware and three control pins. The proposed constant test vectors which are sufficient to detect both the transition and stuck-at faults in the multiplier circuits can be derived directly without any requirement of an ATPG tool. As the GF(2m) multipliers have found critical applications in public key cryptography and need secure internal testing, a built-in self-test (BIST) circuit is proposed for generating test patterns internally. This obviates the need of having three extra pins for the control inputs and also provides public-key security in cryptography. Area and delay of the testable circuit are analyzed using 0.18mum CMOS technology library from UMC

In deep sub-micron regime, interconnect delays dominate VLSI circuit design. Thus, construction of cost-effective global routing trees is key to such designs. In order to reduce the interconnect delay, traditional Manhattan (M-) routing architectures are currently being replaced by the diagonal X architectures. A recent routing architecture is based on Y interconnects, involving the pervasive use of 0deg, 60deg, and 120deg oriented global and semi-global wirings. Unlike the X-routing, Y-routing Is observed to support regular routing grid, which as important for simplifying manufacturing processes and routing and design rule checking algorithms. In this paper, we propose a novel Y-routing algorithm which can solve reasonably sized problems in nominal time. The proposed method is capable of finding routing solutions for problem instances which could not be solved in reasonable time by some recently reported methods. Moreover, it can be easily extended for routing with any uniform orientation

Sensor network has been identified as the most important technology for the next century. Despite of its potential application, wireless sensor network encounters resource restrictions such as low computational power, reduced bandwidth and specially limited power resource. This work reports a network monitoring protocol to provide a logical topology for an energy efficient maximally covered ad-hoc sensor network (Eemca). It is developed around the regular structure of 1-dimensional cellular automata. The simulation results establish that the monitoring of sensor nodes with the proposed technique shows better utilization of the resources that effectively leads to an energy efficient maximally covered sensor network topology.

Testable design for detecting stuck-at and bridging faults in Programmable Logic Arrays (PLAs) based on Double Fixed-Polarity Reed-Muller Expression (DFPRM) is proposed. DFPRMs are generalized expressions of FPRM. It has advantages of compactness and easy testability. The EXOR part in the proposed design is implemented with tree structure that admits a universal test set. For an n-variable function, this design can be tested by (2n+8) test vectors, which are independent of the function and the circuit-under-test (CUT). Excepting a few intergate bridging faults in the EXOR-tree, it detects all other single bridging (both OR-and AND-type) and all single stuck-at faults. This tree based implementation reduces circuit delay significantly compared to cascaded EXOR-part.

This paper reports a scheme for cost optimal design of PRPG, built around nonlinear cellular automata (CM). The characterization of 3-neighborhood CA rules provides the foundation of designing the n-bit PRPG in linear time. The GA (genetic algorithm) framework proposed to evolve the CA results in a minimal cost PRPG structure, in terms of area overhead and delay

A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design and uses only 2-input AND-OR gates. General symmetric functions are then realized following a unate decomposition method. The synthesis procedure guarantees complete and robust path-delay fault testability in the circuit. Experimental results on several symmetric functions reveal that the hardware cost of the proposed design is low, and the number of paths in the circuit is reduced significantly compared to those in earlier designs. Results on circuit area and delay for a few benchmark examples are also reported.

Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of single-input-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The average length of the test sequence (TS) in an n-input CUT is (n+1).2/sup n/ [(n+1).2/sup n-1/] in a fault-free [faulty] condition. The response analyzer (RA) is also simple to design. All robustly testable multiple stuck-open faults (occurring simultaneously both in n- and p-parts) can be detected using the proposed BIST scheme.