Biomedical sensors operate under low supply voltage, in low frequency domains, and require low power consumption. This paper proposes a new power-efficient, low-pass and band-pass fully differential biquad suitable for bio-signal acquisition, based on Folded Gain Boosting Source-Follower (FGB-SF). This solution does not require a Common-Mode Feedback (CMFB) and it offers a wide tuning range. Implemented using 0.18 μm TSMC technology, it achieves the lowest power consumption reported in the literature (0.46 nW), a high Dynamic Range (DR) of 43.8 dB, and an IIP3 of 6.55 dBm with 250 Hz bandwidth. Post-layout simulations demonstrate stability under Montecarlo and PVT variations. The occupied area is only 69.5 μm x 51.3 μm and exibits the lowest FOM compared with the state of the art.

Bioimpedance spectroscopy allows determining the characteristics of a medium through its electrical response. In dynamic events, the approach based on sequential bioimpedance analyses at different frequencies is not appropriate due to its duration. Simultaneous multi-sine spectroscopy is a suitable alternative to obtain the bioimpedance spectrum in a fast way. The practical implementation of this technique requires the design of programmable filters, which include tunable transconductors, for the separation of the different frequency components of the response signal. Two circuit techniques to design a transconductor with tunable transconductance ( G m ), are proposed. The originality of the solution relies on the subtraction of the G m of two voltage-to-current sections, thus leading not only to a wide tuning range of the effective G m but also to a low value of this circuit parameter. The transconductors were designed and fabricated in 180 nm CMOS technology to operate with 1.8 V. Measurements on 9 samples of the silicon prototypes show that mismatch prevents achieving the very low G m obtained in simulations, even though the deviations are within the variation ranges determined by a Montecarlo analysis. The SF and DP solutions display mean values for the maximum/minimum G m of 10.29 μ A/V/149.5 nA/V and 10.1 μ A/V/302.8 nA/V, respectively, which represent transconductance tuning ratios of 68.8 × and 33.4 × , also respectively. Other remarkable feature of this proposal is that the second-order transconductor-capacitor ( G m - C ) bandpass filters (BPFs), designed for signals separation, incorporate multiple-output versions of the proposed transconductors, thus leading to a reduction of area occupation and power consumption. The BPFs were designed to have nominal values of the gain at the centre frequency and of the quality factor of 0 dB and 2.83, respectively, whereas the centre frequency can be programmed over approximately one decade.

Nonlinear calibration allows enhancing the performance of analog and radiofrequency circuits by digitally correcting nonlinearities. Often, calibration is performed in the complex baseband domain, and Volterra models are used. These models have hundreds of coefficients, and easily become computationally unfeasible. This is worse in complex Volterra models, because high-order Volterra terms require summing multiple products of the input signal. We propose a generalized complex Volterra model based on one relaxation of Volterra theory: all the nonlinear monomial terms in the model are considered separately, even if they correspond to a single real coefficient in complex Volterra theory. This produces more accurate models, though with a larger number of coefficients. We thus extensively prune the model by means of OMP and OBS techniques. The resulting models have fewer coefficients and/or better accuracy than conventional Volterra models, resulting in a significantly improved accuracy-complexity trade-off. These results are validated in the experimental calibration of a commercial IF amplifier. The resulting model achieves the same accuracy, with 9 free parameters and 34 multiplications, as the standard Volterra model with 12 parameters and 266 multiplications, resulting in a 25% reduction in the number of parameters, and an 87% reduction in the number of multipliers.

High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasing filters in the multi-GHz range. Asynchronous Time-Interleaved (ATI) digitizers also need low-pass filters before digitization, and additional requirements on their design are set by this specific application. In integrated solutions, inductor-less filters are important for minimizing the chip area footprint. In this paper, we present the design of a 6th-order inductor-less 10GHz low-pass filter implemented in the STMicroelectronics SiGe BiCMOS55 process. It can be used as anti-aliasing filter for conventional 30GS/s digitizers or at the output of a 40GS/s ATI digitizer. We exploit positive feedback to synthesize the active inductor based on a stacked topology, minimizing the number of current branches, and thus power consumption. Analysis and design guidelines for the biquad are presented. The filter exhibits a bandwidth of 10GHz with a power consumption of 43mW, a THD of −45dB and an SNR of 43dB with an input amplitude of 710mV peak-to-peak differential. Extensive corner and Monte Carlo post-layout simulations have been carried out to highlight the robustness of the circuit to PVT and mismatch variations. Experimental results have confirmed very good agreement between measured and simulated performance, validating the proposed design flow.

A CMOS differential amplifier cell for minimum supply requirements is presented. The solution uses transistors in strong inversion and an original biasing scheme that exploits the bulk terminals of the transistor pair to accurately set the quiescent current and provide common-mode control. As a result, we avoid the use of the tail current source adopted in traditional differential stages. An implementation based on an auxiliary switched-capacitor network used in the feedback control loop is proposed and theoretically examined. Measurements on a prototype fabricated in a standard 0.35- mum technology (with threshold voltages around 0.5 V) and powered with 1.2 V show an error in the bias current of about 15% with respect to the expected value. It was found that the obtained overall performance is comparable to that of a traditional long-tailed differential pair that uses a higher supply of 1.5 V.

In this paper we present a gain enhancement technique for very low-voltage deep sub-micron amplifiers based on the use of a CCH-based negative impedance converter. Relaxed specifications on the current conveyor allow an easy implementation of this technique in a sub-1 V environment, where common topologies such as the cascode and the differential pair cannot be used. An example implementation in a 65-nm CMOS technology, using plusmn0.35 V supply voltage and a simple 6-transistor CCH topology, shows a 15.5-dB gain enhancement with a good robustness against process variations.

Pipeline analog-to-digital converters (ADC) are widely used to achieve high resolution and moderately high sampling frequency. In typical implementations, linearity is often limited by capacitor mismatch and finite amplifier gain. The impact of these non ideal effects on the overall linearity of the ADC has been addressed in this paper, obtaining a model to estimate total harmonic distortion (THD), given capacitors' sizing and amplifiers' gain. This model enables the designer to analyze the impact of error sources in each stage separately, and to perform Monte Carlo simulations. In this way, design rules can be obtained to properly size each multiplying digital-to-analog converter (MDAC) in the first stages of the design process.

We propose a linearization technique, for CMOS differential pairs employing resistive source degeneration, which exploits the bulks of the pair as additional control terminals. Simulations were performed using a 0.25-μm process, on an example design powered with 2.5V and 1 mA. Compared to the traditional source-degenerated transconductor, the proposed approach allows a THD reduction in the voltage-to-current conversion by 10dB, for an input differential signal of 0.5Vppand for frequencies up to 100MHz.

A behavioral model of a sample-and-hold circuit is presented, focused on the distortion due to the nonlinear switch on-resistance. A simplified expression for third-order harmonic distortion has been derived, by using a quadratic MOS model where body effect is neglected, and it has been extended to the case of a transmission gate switch. Both the behavioral model and the distortion estimation have been validated by comparison with Cadence simulations, and very low errors have been obtained over a wide range of circuital and signal parameters

We propose an inverting closed-loop amplifier architecture providing high input impedance and a theoretically zero gain error, without requiring infinitely large loop gain. The architecture is based on two nested amplifiers closed in feedback through a resistive network. A straightforward CMOS implementation is also given. Simulations using a 0.35-mum CMOS process are found in agreement with expected results. Monte Carlo simulations have also shown the robustness of the proposed approach against process tolerances