This paper proposes a novel digital voltage regulator architecture for System-on-Chip (SoC) applications. The architecture includes an Analog Nested Loop, which improves the regulator's performance. Implemented in 28nm technology, the regulator occupies an area of 0.011mm2and has a total capacitance of 10.6pF. Measurement results show a Power Supply Rejection Ratio (PSRR) of -44dB at 1MHz and a voltage ripple of 3.61mVpp when the Analog Nested Loop is enabled. The regulator is also tested with a Phase-Locked Loop (PLL) oscillator, and the resulting PLL Phase Noise and Jitter are compared to those obtained with an external, clean supply source. Specifically, the Phase Noise at 100kHz improves from - 96dBc/Hz to -97.5dBc/Hz, and the absolute Jitter improves from 97psrms to 95psrms, when the Analog Nested Loop is enabled.

We report on the development of a time-domain numerical modeling framework to estimate timing jitter in High-Speed Serial Interfaces (HSSI) including a wide range of effects such as Inter-Symbol Interference (ISI) due to channel dispersion, phase noise of transmitter (TX) and receiver (RX) frequency synthesizers and use of bang-bang phase detector in the Clock and Data Recovery (CDR) loop. Based on the step response of the channel, the numerical model computes the response of the system to a random sequence of bits and provides information in terms of eye diagram, bathtub plot and jitter histogram. Different definitions of jitter are investigated, and for each of them we consider the physical effects that are included, eventually identifying that the most complete definition is based on the time distance between the edges instants defined by the CDR and the crossing points of the sampled signal. We also found that this definition is consistent with the features of the bathtub plot. A channel compliant with the PCIe 4.0 standard is used as test vehicle, including the main equalization strategies. The numerical model is then compared to a simple analytical model for the CDR jitter that can be augmented by including Data-Dependent Jitter (DDJ). An approach to system-level analysis based on proper combination of the above elements is eventually proposed to provide quick although accurate aid to the design of CDRs in HSSIs.

Despite the scaling of the supply voltage of deep-submicrometer CMOS technologies, many applications still require to deal with off-chip signals in high-voltage domains (e.g., 3.3 and 5 V). Hence, foundries offer fabrication processes with voltage-tolerant transistors, which are inherently protected from the electrical stress, at the expenses of compromising their performances, reducing the design portability, and augmenting the production costs in case of the customization of the process. As an alternative, circuit techniques, such as cascoding, adaptive biasing, and voltage shifting, result effective in designing analog circuits, such as amplifiers and voltage drivers at high supply voltage with voltage-scaled transistors. This article presents the architecture of a switch for analog multiplexers (MUXs) able to handle signals up to twice the nominal supply voltage of the employed transistors. To validate the circuit choice, a switch for a 5-V MUX has been designed with 2.5-V transistors in 28-nm CMOS technology. The comparison with a benchmark architecture with tailored 5-V devices shows that an about three times larger area and 4-$\mu \text{A}$static current demand have to be considered. Moreover, an accelerated degradation test (ADT) showed a similar decay of the features of both types of switches.

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required.

This article proposes compact expressions for the jitter in clock and data recovery (CDR) circuits based on bang-bang phase detector including the phase noise of the transmitter and receiver oscillators as well as the quantization noise associated with the finite number of phases of the phase interpolator (PI) that align the receiver clock to the incoming data. Different approaches to perform the Early/Late detection on deserialized data and edge samples are compared: the use of majority voting degrades the CDR bandwidth, increasing the impact of the clock jitter on the CDR jitter; on the other hand, counting the single Early/Late occurrences does not degrade the bandwidth but increases the noise related to the finite phases of the PI. The proposed analytical formulas are validated against event-driven behavioral simulations of the CDR system including free-running oscillators as well as phase-locked loop (PLL) for clock generation.

Performance of FMCW generators based on DPLLs are significantly affected by the presence of spurs. The latter may originate from the inherent operation of the DPLL itself, when operated in Fractional-N mode, or by external aggressors via coupling paths. Moreover, non-linearities of the loop can result in a worsening of the spur level thus in a degradation of the generated frequency modulation. This paper provides an insight on spurs impact in PLL-based chirp generators for radar sensors. Three different scenarios are taken into account: fractional spurs arising from non linearities, spurs coupling to the output of the DPLL and coupling of the digital activity of the divider to the DCO. The analysis is performed by means of a time-domain model of the FMCW Radar transceiver for target detection, and the effect on the range FFT and on Doppler shift of the base-band signal is presented.

Robust and reliable operation of high-speed serial interfaces (HSSI) in automotive environment is challenging. In this paper, we present the analysis and design of a 10Gbps receiver with 4-taps decision feedback equalizer (DFE) with 1-tap unrolled. A novel clock-and-data-recovery (CDR) algorithm is presented to consistently deal with the combined effect of Inter-Symbol Interference (ISI) and DFE on data transitions. The receiver, designed with a 28nm technology, consumes 2.05mW/Gbps and post-layout simulations are reported to show the advantage of the proposed architecture.

The need for low-noise, highly-linear, programmable chirp generators makes digital phase-locked loops (DPLLs) an attractive solution for radar sensors. This paper presents a general analysis and comparison of the two main techniques enabling wideband frequency modulation (FM) in PLLs, namely the two-point injection and the pre-emphasis. It is shown that while the two topologies are equivalent in term of mismatch error suppression, the required input range for the time-to-digital converter (TDC) is substantially lower in the two-point injection scheme, thus relaxing the TDC power consumption and linearity.