Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low power. In such architectures, inter-partition communication over global wires has a significant impact on overall processor performance and power consumption. VLSI techniques allow a variety of wire implementations, but these wire properties have previously never been exposed to the microarchitecture. This paper advocates global wire management at the microarchitecture level and proposes a heterogeneous interconnect that is comprised of wires with varying latency, bandwidth, and energy characteristics. We propose and evaluate microarchitectural techniques that can exploit such a heterogeneous interconnect to improve performance and reduce energy consumption. These techniques include a novel cache pipeline design, the identification of narrow bit-width operands, the classification of non-critical data, and the detection of interconnect load imbalance. For a dynamically scheduled partitioned architecture, our results demonstrate that the proposed innovations result in up to 11% reductions in overall processor ED/sup 2/, compared to a baseline processor that employs a homogeneous interconnect.

We present an overview of the SCIRun2 parallel component framework. SCIRun2 is based on the common component architecture (CCA) as stated by R. Armstrong et al. (1999) and the SCI Institutes' SCIRun by C. Johnson and S. Parker (1999). SCIRun2 supports distributed computing through distributed objects. Parallel components are managed transparently over an M/spl times/N method invocation and data redistribution subsystem. A meta component model based on CCA is used to accommodate multiple component models such as CCA, CORBA and Dataflow. A group of monitoring components built on top of the TAU toolkit as stated in Advanced Computing Laboratory (1999) evaluate the performance of the other components.