We propose a novel real-shared memory module with multiports which is called "RSMM" to overcome the bus bottleneck problem in a parallel processor system with shared memory. The testing processor can be directly connected to this RSMM via its multiport interface without conventional common bus. It is the characteristic of the design to utilize the high bandwidth "multiport ring-bus" architecture in order to achieve high speed data transfer inside the RSMM. The RSMM has 8 ports. Therefore it can provide data sharing for 8 peripheral equipments (PE) simultaneously. The peak of the transfer throughput can achieve 3.2 Gbytes/s. The basic operation of the RSMM is confirmed by simulation and the result shows that the system performance with the RSMM is superior to that with conventional common buses.

A parallel images processing field programmable gate array (FPGA) for real time image processing system has been proposed to realize high image processing speed and flexibility. This FPGA has a small size configuration memory. In addition, a parallel reconfigurable interconnection network and logic blocks have been used in this FPGA. A test chip was designed and fabricated using 0.35 /spl mu/m CMOS technology. It was confirmed in the test chip that the reconfiguration of the image processing is successfully performed.

The smart VISIOn chip has a large potential for application in general purpose high speed image processing systems. In order to fabricate smart vision chips including photo detector compactly, we have proposed the application of three dimensional LSI technology for smart vision chips. Three dimensional technology has great potential to realize new neuromorphic systems inspired by not only the biological function but also the biological structure. In this paper, we describe our three dimensional LSI technology for neuromorphic circuits and the design of smart vision chips .

We describe a new multiport memory which is called Shared DRAM (SHDRAM) to solve bus-bottle neck problem in parallel processor system with shared memory. This SHDRAM has four ports. Therefore four processors can be directly connected to this memory without bus-bottle neck. The basic operation of SHDRAM is confirmed by computer simulation and measurement results.