Demo Data from EDBT 2026 / reviewers in the wild / expert
Wayne A. Wong
dblp:23/4201
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 73% Performance modeling and evaluation · 21% Processor architecture and microarchitecture · 6% | |
| Software engineering, system software, and programming languages
1 paper |
Runtime systems and virtual machines · 100% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.0 | 1 | 2000 | Modified LRU Policies for Improving Second-Level Cache Behavior · HPCA 2000 |
Memory systems › cache management
cache replacement |
0.0 | 1 | 2000 | Modified LRU Policies for Improving Second-Level Cache Behavior · HPCA 2000 |
Runtime systems and virtual machines
interpreter |
0.0 | 1 | 1996 | The Structure and Performance of Interpreters · ASPLOS 1996 |
Runtime systems and virtual machines › interpreter
interpreter performance |
0.0 | 1 | 1996 | The Structure and Performance of Interpreters · ASPLOS 1996 |
Performance modeling and evaluation
workload characterization |
0.0 | 1 | 1996 | The Structure and Performance of Interpreters · ASPLOS 1996 |
Methods — techniques the papers use, named apart from their topics
performance measurement · 0.0benchmarking · 0.0temporal locality detection · 0.0profile-based trace analysis · 0.0online locality table · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | Modified LRU Policies for Improving Second-Level Cache BehaviorabstractMain memory accesses continue to be a significant bottleneck for applications whose working sets do not fit in second-level caches. With the trend of greater associativity in second-level caches, implementing effective replacement algorithms might become more important than reducing conflict misses. After showing that an opportunity exists to close part of the gap between the OPT and the LRU algorithms, we present a replacement algorithm based on the detection of temporal locality in lines residing in the L2 cache. Rather than always replacing the LRU line, the victim is chosen by considering both its priority in the LRU stack and whether it exhibits temporal locality or not. We consider two strategies which use this replacement algorithm: a profile-based scheme where temporal locality is detected by processing a trace from a training set of the application and an on-line scheme, where temporal locality is detected with the assistance of a small locality table. Both schemes improve on the second-level cache miss rate over a pure LRU algorithm, by as much as 12% in the profiling case and 20% in the dynamic case. Wayne A. Wong, Jean-Loup Baer |
HPCA | 1 |
| 1996 | The Structure and Performance of InterpretersabstractInterpreted languages have become increasingly popular due to demands for rapid program development, ease of use, portability, and safety. Beyond the general impression that they are "slow," however, little has been documented about the performance of interpreters as a class of applications.This paper examines interpreter performance by measuring and analyzing interpreters from both software and hardware perspectives. As examples, we measure the MIPSI, Java, Perl, and Tcl interpreters running an array of micro and macro benchmarks on a DEC Alpha platform. Our measurements of these interpreters relate performance to the complexity of the interpreter's virtual machine and demonstrate that native runtime libraries can play a key role in providing good performance. From an architectural perspective, we show that interpreter performance is primarily a function of the interpreter itself and is relatively independent of the application being interpreted. We also demonstrate that high-level interpreters' demands on processor resources are comparable to those of other complex compiled programs, such as gcc. We conclude that interpreters, as a class of applications, do not currently motivate special hardware support for increased performance. Theodore H. Romer, Dennis Lee 0001, Geoffrey M. Voelker, Alec Wolman, Wayne A. Wong, Jean-Loup Baer, Brian N. Bershad, Henry M. Levy |
ASPLOS | 5 |