Feedback amplifiers consisting of multiple gain stages are used to establish highly accurate buffered/amplified signals that can drive a wide range of capacitive load (CL). This article models, analyzes, and presents the measurement results of a high-gain four-stage operational transconductance amplifier (OTA) that is able to handle a wide range of CL up to infinity. In addition to local compensation capacitors and nulling resistors in the intermediate stages, two high-speed feedback loops made by parallel Miller capacitors and current buffers provide Miller compensation and the consequent pole-splitting in the lower CL range. The dominant pole is made dependent on the CL for the higher CL range, enabling the maintenance of the stability conditions up to infinite CL. The proposed amplifier was integrated into a 65-nm CMOS technology, consuming 140-$\mu$A static current under a 1.2-V supply and an active area of 0.0086 mm$^{{2}}$. A dc gain greater than 100 dB was also perceived with a unity-gain frequency (UGF) of 4.09, 2.01, and 0.27 MHz for 4.7, 10, and 100-nF load capacitors, respectively. The average slew rate (SR) is 0.59 V/$\mu$s, when the OTA is formed as a buffer targeting the CLs higher than 4.7-nF.

A modified circuit-level strategy to improve the speed/stability trade-off of low-dropout regulators is presented. The technique, called hybrid-cascode compensation, is applied to stabilize the regulation loop. When designed carefully, results prove the efficacy of this method in minimizing output settling time under various transient conditions. Equivalently, power consumption and/or die area can be minimized for the same settling time. Employing this technique, a 0.7V-10mA voltage regulator with a minimum line voltage of IV has been designed in 90nm CMOS technology. With improved settling time, stability is guaranteed for load capacitors as low as 50pF. Power supply rejection is always better than -30dB for all frequencies.

A modified circuit topology for bandgap references capable of providing very high load current with output which has small sensitivity against temperature variations is presented. Employing a proportional-to-absolute-temperature (PTAT) current source and a complementary-to-absolute-temperature (CTAT) voltage source in a novel closed-loop configuration, the output voltage can be tuned over a wide range of voltages lower or higher than Silicon bandgap voltage of 1.2 V. These features make the configuration a promising competitor for low-dropout regulators. Low-power and low-voltage design considerations of the circuit offering many advantages are addressed. With different specifications, two design examples in 0.18-yKm standard CMOS technology are reported. Thanks to a modified amplifier topology, the 0.9 V and 1.3 V bandgap references have fast stable operation for the load currents ranging from 0 mA to 100 mA with load capacitors as low as 10 pF and no equivalent series resistance (ESR). Simulated values of the temperature coefficient for both design cases are smaller than 37ppm/°C.

Optimization of power consumption is one of the main design challenges in today's low-power high-speed analog integrated circuits. In this paper, two popular techniques to stabilize two-stage operational amplifiers, namely Miller and cascode compensations are compared from power point of view. To accomplish this, the cascode-compensated structure is basically analyzed to derive the required equations for comparison. The results show that for the same specifications, cascode compensation is more power efficient than Miller compensation especially for heavy capacitive loads. This has been confirmed by circuit-level simulations in 0.25μm CMOS technology.

Design of low-voltage high-resolution MOSFET-only pipeline analog to digital converters (ADCs) has been investigated in this work. The nonlinearity caused by replacing linear MIM capacitors with compensated depletion-mode MOS transistors in all 1.5-bit residue stages of the ADC has been properly modeled to be calibrated in digital domain. The proposed calibration technique makes it possible to digitally compensate the nonlinearity of a 1.8V 12-bit 65MS/s MOSFET-only ADC in 0.18 mum standard digital CMOS technology. It improves the values of signal-to-noise-plus-distortion-ratio (SNDR) and spurious-free dynamic range (SFDR) by approximately 27dB and 35dB respectively

Considering the importance of settling behavior of operational amplifiers (opamps) for a given accuracy in many applications, an efficient methodology for the design of high-speed two-stage opamps, based on settling time, is proposed in this paper. Concerning the application of the opamp, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. Simulation results are presented to show the effectiveness of the methodology.

In this paper, a heuristic methodology for design of highly linear MOSFET capacitors (MOSCAPs) has been presented. For a certain amount of accessible chip area, the proposed algorithm intends to find the structure which has the least C-V variation. It uses a modified version of the genetic programming to optimize the capacitor topology and transistors' dimensions. To test the performance of the algorithm, it was utilized for obtaining a highly linear 1 pF capacitor, i.e. with less than 3% variation of capacitance versus 1 V variation across the MOSCAP structure terminals, in a commercial 0.18 μm standard digital CMOS technology. This level of linearity can be otherwise achieved only with MIM capacitors, which are not available in digital CMOS processes.

In this paper, a new topology for CMOS current steering DAC, i.e. folded current-steering structure, suitable for low-voltage applications is presented. Using the folded structure, more voltage headroom is available for the current-source devices increasing the output impedance of the current sources. The DAC linearity is thus improved. Also this novel topology improves the value of PSRR and output voltage swing without SFDR degradation and results in more constant load for current cell. Also a current-steering logic decoder with differential outputs is suggested. Besides, gain boosting is applied to increase the output impedance of current source. These techniques are used to design a 12-bit 200MS/s DAC with 1.5-V power supply and more than 72dB SFDR is achieved in all frequencies. Also Monte-Carlo simulations show that the probability of an SFDR of more than 65dB is more than 90% for an input frequency of 100MHz