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Trudi Mewett

dblp:23/5130 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 75% Integrated circuit design · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › power integrity
decoupling capacitance allocation		 0.112007
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise · DAC 2007
Integrated circuit design
low-power circuit design		 0.112007
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise · DAC 2007
Electronic design automation
physical design		 0.112007
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise · DAC 2007
Electronic design automation › physical design › power delivery network design
power/ground network optimization		 0.112007
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise · DAC 2007

Methods — techniques the papers use, named apart from their topics

linear programming · 0.1decap budgeting · 0.1
YearPublicationVenuePosition
2007 On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise
abstract
Decap allocation are the primary methods for addressing the dynamic voltage noise problem of on-chip power networks. When space in the immediate proximity of a hot spot is constrained, simply adding decoupling capacitance without improving the local wiring is ineffective. Based on this key observation we proposed an effecient co-optimization of decap allocation and local wiring enhancement. The method solves a linear program (LP) iteratively and is based on the decap budgeting algorithm [10]. Experimental results on two actual chip designs demonstrate the area and run-time efficiency of the co-optimization algorithm. Moreover, it provides excellent solutions even in cases where decap allocation alone fails to provide a feasible solution.
Min Zhao 0001, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
 DAC5