This paper presents the design and analysis of a family of voltage reference generators (VRGs) based on the stacking of a current-source transistor MIand a resistive-load transistor MR, i.e., stacking of MI,R(SMIR) in standard CMOS technology for sub-1V and sub-nW operation. Design guidelines are provided to obtain the reference voltage for various temperature characteristics, namely proportional to absolute temperature (PTAT), complementary to absolute temperature (CTAT), and constant with temperature (CWT), by appropriately sizing the two transistors as current source and load respectively. The proposed 6 such SMIR VRGs in 65nm consume an average power less than 4pW and occupy an area less than 30µm × 100µm when measured from 20 different samples. All VRGs operate at a minimum supply voltage of 0.4V and achieve an average line regulation better than 0.3%/V. For the CWT VRGs, an average temperature coefficient better than 260.9ppm/°C is achieved from -20°C to 80°C.

This paper introduces a conversion matrix method for linear periodically time-variant (LPTV) digital phase-locked loop (DPLL) phase noise modeling that offers precise and computationally efficient results to enable rapid design iteration and optimization. Unlike many previous studies, which either assume linear time-invariance (LTI) and therefore overlook phase noise aliasing effects, or solve LPTV systems with noise folding and multiple sampling rate conversions that heightens modeling and computational complexity, the proposed conversion matrix method allows the designer to represent LPTV systems using intuitive LTI-like transfer functions with excellent accuracy. Additionally, the uncorrelated upsampling method addresses the cross-correlated spectrum of cyclostationary noise sources by a simple matrix multiplication. This eliminates the need to consider the beat frequency of the upsampled noise source and the system with different sampling rates, thus improving computational efficiency. The proposed algorithm is applied to modeling a integer-N DPLL with time-varying proportional loop gain, and the modeling accuracy is validated with Simulink transient simulations.

Multiscale dynamics of neural and metabolic interactions implicated in disease states call for precision electrophysiology to resolve a variety of biopotential signals across the body that cover a wide range of frequencies, from the mHz-range electrogastrogram (EGG) to the kHz-range electroneurogram (ENG). Currently available integrated systems for unobtrusive and minimally invasive electrophysiology suffer from tradeoffs between bandwidth coverage, noise floor, power consumption, and input impedance, which limits their detection range and accuracy. Here we present a 16-channel wide-band ultra-low-noise neural recording system-on-chip fabricated in 65nm CMOS for chronic use in mobile healthcare settings that covers 0.001 Hz to 1 kHz bandwidth through sample-level duty-cycling. Each channel consists of a delta-sigma analog-to-digital converter (ADC) achieving$\mathbf{1.0}\ \mu \mathbf{V}_{rms}$input-referred noise over 1 Hz - 1 kHz bandwidth with a Noise Efficiency Factor (NEF) of 2.93 in continuous operation mode, while power duty-cycling of the biasing and clocks maintains consistent low input-referred noise levels down to 0.001 Hz sampling rates at$\mathbf{435}\ \mathbf{M}\Omega$input impedance. In vivo recordings from the chip interfacing to electrodes mounted on the forehead resolving slow-wave electroencephalogram (EEG) biopotentials demonstrate proof-of-concept functionality.

This paper describes an ultra-low-power low-noise amplifier (LNA) targeting the 617-652 MHz narrowband-IoT (NB-IoT) frequency band. The design breaks the trade-off in practice between the input matching, minimum required DC current, and minimum NF by using a step-down transformer with an equivalent turns ratio of less than 1, resulting in input impedance boosting and noise attenuation of the main transistor. A local feedback loop is also employed to use the LNA current source transconductance to further attenuate the main transistor noise without additional power cost. The LNA power consumption scales efficiently with the required overall transconductance without being limited to the input matching condition, in practice, while enabling a sub-3dB minimum NF, making it a suitable option for a wide range of applications. A comparison between the proposed, conventional, and state-of-the-art low-power LNA structures is presented with both analytical and simulation models, while measurement results of a prototype designed in a 65 nm technology show a sub-3dB minimum noise figure (NF), −8.8 dBm IIP3, 15 dB gain, and a state-of-the-art FoM of 39.74 dB while consuming only 36$\mu \text{W}$from a 0.55 V supply.

This paper analyzes the ability to suppress in-band noise power of a regenerative amplifier (RA) operating in the nonlinear regime in response to a continuous wave (CW) input tone. As opposed to the linear regime where a CW tone and the noise floor experience the same transfer function, it is shown that the non-linear saturation behavior of an RA yields different transfer characteristics between a CW tone and noise, ultimately leading to an improvement in the output carrier-to-noise ratio (CNR). This is all thanks to the high gain, narrow bandwidth, and the compressive third-order nonlinearity of the RA. This non-linear noise suppression is first analyzed mathematically using single tones in the frequency domain to represent the signal and the noise. Then, simulation of an RA circuit model is shown to be in excellent agreement with the analytical results. Lastly, a discrete RA has been implemented to experimentally verify the noise-suppression phenomenon. The measurement results clearly demonstrate noise suppression and show an output CNR improvement of up to 3 dB. Potential applications of the RA with noise suppression are also discussed.

This study presents a new QRS detection algorithm making use of the background noise that is inevitably present in electrocardiogram (ECG) recordings. The algorithm suppresses noise, enhances the QRS-waves, and applies a threshold for QRS detection. Noise suppression and QRS enhancement are performed by a band-pass filter stage followed by a nonlinear stage based on the interaction of a particle inside an underdamped monostable potential well. The nonlinear stage maximizes the output when there is a QRS-wave and minimizes the output otherwise. One of the instruments that the nonlinear stage uses to enhance the QRS-waves is stochastic resonance, where the output is maximized for a non-zero intensity background noise. In terms of QRS-wave detection F1 score, which ranges from 98.87% to 99.99% on four major benchmarking databases (MIT-BIH Arrhythmia, QT, European ST-T, and MIT-BIH Noise Stress Test), the algorithm outperforms all existing ECG processing algorithms. The study, for the first time, demonstrates QRS-enhancement by facilitating stochastic resonance while suppressing in-band noise of ECG signals. Detecting QRS-waves as the ECG data streams, having a complexity of O(n), and not requiring any training data make the algorithm convenient for real-time ECG monitoring applications with limited computational resources.

Ultra-wide band (UWB) technology has emerged as the most reliable, accurate and precise position location system. Due to the wide bandwidth (>500M) of operation, UWB systems exhibit excellent resilience to out-of-band interference from narrowband jammers such as 2G/3G/4G cellular and WiFi. The newly released FR1 5G NR licensed bands (n77, n78 n79) overlap with the 3.2-5GHz portion of the UWB band and are expected to have operating bandwidth of 100-200MHz to meet the rising demand for high data rates. FR1 5G NR is expected to start rolling out in 2020 and densify and extend to 10GHz over the next decade. The ubiquitous presence of wideband 5G NR signals threatens the operation of UWB position location systems. In this paper, we report the preliminary measurement results of the impact of wideband 5G NR jammers on the achievable range of a commercial DecaWave UWB indoor position location system. The measurements results were compared with theoretical prediction obtained by the Cramer-Rao lower bound.

Recent demand and initiatives in brain research have driven significant interest toward developing chronically implantable neural interface systems with high spatiotemporal resolution and spatial coverage extending to the whole brain. Electroencephalography-based systems are noninvasive and cost efficient in monitoring neural activity across the brain, but suffer from fundamental limitations in spatiotemporal resolution. On the other hand, neural spike and local field potential (LFP) monitoring with penetrating electrodes offer higher resolution, but are highly invasive and inadequate for long-term use in humans due to unreliability in long-term data recording and risk for infection and inflammation. Alternatively, electrocorticography (ECoG) promises a minimally invasive, chronically implantable neural interface with resolution and spatial coverage capabilities that, with future technology scaling, may meet the needs of recently proposed brain initiatives. In this paper, we discuss the challenges and state-of-the-art technologies that are enabling next-generation fully implantable high-density ECoG interfaces, including details on electrodes, data acquisition front-ends, stimulation drivers, and circuits and antennas for wireless communications and power delivery. Along with state-of-the-art implantable ECoG interface systems, we introduce a modular ECoG system concept based on a fully encapsulated neural interfacing acquisition chip (ENIAC). Multiple ENIACs can be placed across the cortical surface, enabling dense coverage over wide area with high spatiotemporal resolution. The circuit and system level details of ENIAC are presented, along with measurement results.

As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.

Wearable systems show considerable promise in monitoring and assessing the real-time performance of athletes, the health status of patients, or the general well-being of interested users. Most wearables today focus on monitoring physical parameters (e.g., activity, respiration rate, etc.), or electrophysiology (e.g., ECG, EEG, etc.). In order to augment the richness of collected data, the next-generation of wearables will also be capable of monitoring underlying chemical homeostatis of the user, for example through measurement of glucose in interstitial fluid, lactate in saliva, or electrolytes in sweat. This paper discusses the challenges of building wearable chemical biosensors, including biosensor functionalization, flexible material engineering, bioelectronic integration, and data analytics.

This paper presents a gate-leakage-based supply- and temperature-stabilized current reference generator that can output currents as low as 5 pA with minimal power overhead. The output reference current is generated by driving a set of gate-leakage transistors designed to have opposing temperature coefficients with a stabilized voltage reference. Low-power operation is achieved by generating the voltage reference via a novel two-stage, 4T push-pull structure that can operate at a low supply voltage, and driving this reference to the gate-leakage transistors via a low-voltage self-biased amplifier. Designed in a 65 nm CMOS process, the proposed current reference generator is simulated to consume 14.5 pW at a 0.5 V supply voltage. Due to the push-pull structure and complementary gate-leakage transistors, the design achieves a temperature stability of 31 ppm/°C from 0 °C to 100 ° C, and a line sensitivity of 0.94%/V averaged across 500 Monte Carlo samples, thereby enabling an ultra-low-power, area-efficient, and temperature- and supply-stabilized current reference solution at pA-levels.

Conventional EEG systems are extremely power hungry due to a reliance on high resolution analog-to-digital converters (ADCs) to cover their required dynamic range. This paper presents a novel architecture for acquiring multi-channel high-resolution EEG using low power techniques. Instead of digitizing the output of each analog front-end (AFE) amplifier with an individual ADC, a voltage-controlled oscillator is used to generate an up-converted frequency-modulated (FM) signal at a unique carrier frequency. All channels then share a single wire via frequency-domain multiplexing (FDM), enabling a rugged mechanical design. The composite FM signal is then digitized with a single ADC optimized for time-domain resolution (1 MHz, 12 bits) rather than employing multiple ADCs optimized for voltage-domain resolution (1 kHz, 16–24 bits), thereby enabling a low-power implementation. To validate this approach, a discrete prototype is developed and achieves 75 dB of dynamic range per channel.

This paper introduces a modeling framework to predict the efficiency scaling of switched-capacitor (SC) dc-dc converters under power density constraints. A reference power density metric is introduced under which SC converters are integrated directly on silicon using the available decoupling capacitance without increasing the chip footprint. An analytical model is then employed to predict the scaled SC converter efficiency, where it is found that the efficiency scales inversely with the product of the chip clock frequency and the MOSFET intrinsic delay. Through a derived numerical model of the SC power density, it is shown that a ~ 0.5 W/mm2SC density is sufficient to satisfy portable SoC power management needs with over 80% SC efficiency across the International Technology Roadmap for Semiconductors. This is at minimal area penalty by utilizing the nominally required 0.5 nF/mm2decoupling capacitance for supply integrity.

SUMMARY This paper is about using the existing Monte Carlo approach for pricing European and American contracts on a state‐of‐the‐art graphics processing unit (GPU) architecture. First, we adapt on a cluster of GPUs two different suitable paradigms of parallelizing random number generators, which were developed for CPU clusters. Because in financial applications, we request results within seconds of simulation, the sufficiently large computations should be implemented on a cluster of machines. Thus, we make the European contract comparison between CPUs and GPUs using from one up to 16 nodes of a CPU/GPU cluster. We show that using GPUs for European contracts reduces the execution time by ∼ 40 and diminishes the energy consumed by ∼ 50 during the simulation. In the second set of experiments, we investigate the benefits of using GPUs’ parallelization for pricing American options that require solving an optimal stopping problem and which we implement using the Longstaff and Schwartz regression method. The speedup result obtained for American options varies between two and 10 according to the number of generated paths, the dimensions, and the time discretization. Copyright © 2012 John Wiley & Sons, Ltd.

The aim of this paper is the efficient use of CPU and GPU clusters for a general path-dependent exotic European pricing, and their comparison in terms of speed and energy consumption. To reach our goal, we propose a parallel random number generator which is well suited to the parallelization paradigm, then, we implement a multidimensional Asian contract as a benchmark using g++/OpenMP/OpenMPI on CPUs and CUDA-nvcc/OpenMPI on GPUs. Finally, we give the detailed results of the two architectures for different size problems using 1-16 GPUs and 1-256 dual-core CPUs.

Ultra-wide-band (UWB) communication has a variety of applications ranging from wireless USB to radio frequency (RF) identification tags. For many of these applications, energy is critical due to the fact that the radios are situated on battery-operated or even batteryless devices. Two custom low-power impulse UWB systems are presented in this paper that address high- and low-data-rate applications. Both systems utilize energy-efficient architectures and circuits. The high-rate system leverages parallelism to enable the use of energy-efficient architectures and aggressive voltage scaling down to 0.4 V while maintaining a rate of 100 Mb/s. The low-rate system has an all digital transmitter architecture, 0.65 and 0.5 V radio-frequency (RF) and analog circuits in the receiver, and no RF local oscillators, allowing the chipset to power on in 2 ns for highly duty-cycled operation.

Long distance, low data-rate UWB communication for sensor network applications requires a highly energy efficient transceiver combined with circuit and system-level optimizations to maximize range. A custom pulsed-UWB transceiver chipset in 90 nm CMOS is presented that targets these aggressive specifications. The transceiver efficiently communicates at data rates from 0-to-16.7 Mbps in three 550 MHz-wide channels in the 3.1 to 5 GHz band by using pulse position modulation (PPM). The transmitter uses an all-digital architecture and calibration technique to synthesize pulses with programmable width and center frequency. The non-coherent receiver operates at 0.65 V and performs channel selection Altering, energy detection, and bit-slicing. As FCC regulations limit the maximum transmit power of UWB communication, a run-length limiting technique is presented to reduce energy requirements when maximizing range at low data rates.

It is well known that the use of canonical signed-digit (CSD) multiplier coefficients in combination with sub-expression sharing and elimination leads to a substantial reduction in the hardware complexity of FIR digital filters. This paper presents a genetic algorithm for the design and optimization of frequency-response masking (FRM) FIR digital filters over the CSD multiplier coefficient space. This is based on designing a corresponding infinite-precision-coefficient digital filter seed (through a conventional continuous optimization), and on quantizing the resulting multiplier coefficients into CSD coefficients via a look-up table. The resulting digital filter is subsequently encoded into a chromosome which is perturbed to form an initial population for the genetic algorithm. The salient feature of the resulting genetic algorithm is that it automatically leads to legitimate CSD-coefficient offspring digital filters after the operations of crossover and mutation, i.e. without any recourse to gene repair. Application to the design of a bandpass FIR digital filter produces a CSD-coefficients digital filter with very close performance to that obtained by the corresponding continuous infinite-precision optimization

Double-base number systems (DBNSs) have recently gained recognition for the hardware implementation of low-power digital signal processing systems. This paper presents a genetic algorithm for the design of frequency response masking (FRM) digital filters over a single-digit DBNS system. This is based on designing a corresponding seed infinite precision coefficient digital filter (through continuous optimization), and on quantizing the resulting multiplier coefficients into single-digit DBNS coefficients via a look-up table. The resulting digital filter is encoded into a chromosome which is perturbed to form an initial population for the genetic algorithm. The salient feature of the resulting genetic algorithm is that it automatically leads to legitimate DBNS offspring digital filters after the operations of crossover and mutation, i.e. without any recourse to gene repair. Application to the design of a bandpass FRM digital filter produces a DBNS-coefficients digital filter with superior performance to that obtained by continuous optimization.