Demo Data from EDBT 2026 / reviewers in the wild / expert
V. P. Kirpalani
dblp:23/5979
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 61% Memory systems · 30% Interconnection networks and networks-on-chip · 9% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.0 | 1 | 1996 | A Modified TRAM Architecture · IEEE Trans. Computers 1996 |
Memory systems
DRAM |
0.0 | 1 | 1996 | A Modified TRAM Architecture · IEEE Trans. Computers 1996 |
Electronic design automation › hardware verification and test
memory testing |
0.0 | 1 | 1996 | A Modified TRAM Architecture · IEEE Trans. Computers 1996 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | A Modified TRAM ArchitectureabstractThis paper modifies the tree RAM (TRAM) architecture (Jarwala and Pradhan, 1988) of multimegabit dynamic random access memories using a tree-star (TS) interconnection topology. The modified TS-RAM design offers a reduced access time and an improved yield for the proposed TS-RAM architecture. We also propose an improved built-in self test (BIST) approach for the architecture. Suresh Rai, V. P. Kirpalani |
IEEE Trans. Computers | 2 |