Nowadays, MEMS testing has become a growing problem because it usually needs specific and sophisticated testing equipment and is very time-consuming. To solve this problem, this paper proposes a Built-In Self-Test (BIST) method for membrane MEMS piezoresistive sensor. With the proposed method, an on-chip electric signal can be used as the test stimuli, and process defects of piezoresistive sensor can be diagnosed by analyzing the output response of piezoresistive sensor on chip. The simulation shows that the proposed MEMS BIST scheme can effectively replace the physical testing stimuli with electric signal, thus reduce the dependence on external signal sources and the cost of manufacturing devices.

MEMS devices are expected to be used in a growing number of high-volume and low-cost applications. However because they usually require complex test stimuli rather than simple digital electronic signals as common VLSI systems to verify their specifications, testing and calibration costs have actually become a bottleneck to reduce the overall production cost of MEMS sensors. To address this issue, this paper presents an on-chip scheme to calibrate the responsivity of infrared thermopile temperature sensor with digital control signals. With the proposed method, the responsivity related to the ambient temperature can be calibrated before the target temperature being measured thus to achieve accurate temperature measurement. The proposed self-calibrating thermopile sensor design has been realized by CMOS-compatible process to prove the effectiveness of the self-calibration temperature measurement method.

Test compression has become a de facto technique in VLSI testing. Meanwhile, excessive capture power of at-speed testing has also become a serious concern. Therefore, it is important to co-optimize test power and compression ratio in at-speed testing. In this paper, a novel X-filling framework is proposed to reduce capture power of both LoC and LoS at-speed testing, which is applicable for different test compression schemes. The proposed technology has been validated by the experimental results on larger ITC'99 benchmark circuits.

Large test data volume and high test power consumption are two major concerns for the industry when testing large integrated circuits. Linear decompress or-based compression (LDC) is efficient in reducing test data volume, while X-filling during ATPG can efficiently reduce test power with low overhead. However, traditional X-filling methods cannot be reused in the LDC environment. In this paper, we propose a virtual circuit model to make the linear de-compressor transparent to the external testing. As a result, existing X-filling methods can be reused to reduce test power. Experimental results on benchmark circuits demonstrate the efficiency of the proposed approach.

On-chip linear decompression-based schemes have been widely adopted by industrial circuits nowadays to effectively reduce the ever increasing test data volume and test time. Though they can easily achieve relatively high compression ratio, there is a bound of effective compression ratio for these compression schemes. Prior work tried to address this problem by trying different compression architectures to identify this compression bound. However, they can not predict this compression bound efficiently. In this paper, we will first analyze the correlation between the effective compression ratio and the compression architecture, thus to predict that compression bound efficiently. In addition, this paper will also propose how to design the compression architecture for target effective compression ratio with one-pass calculation, which was usually done by a time-consuming try-and-error process as well in the current DFT flow. Experimental results show the accuracy of the prediction and the effectiveness of the compression architecture design.

This paper proposes to provide testability for the breaking point produced by the Through-Silicon-Vias (TSVs) of 3D-Stacked ICs (3D-SICs) during pre-bond testing with low Design-for-Testability (DfT) cost. Different from prior solutions which utilize two additional wrapper cells for the breaking point at each TSV, this paper proposes to provide the testability of two ends of the TSVs respectively by reusing the existing Primary-Inputs (PIs)/ Primary-Outputs (POs) and Pseudo-PIs/Pseudo- POs (PPIs/PPOs). To further reduce the hardware overhead and enhance the efficiency of the proposed method, this paper has also proposed the metrics and algorithm on deciding the selecting order of the TSVs and the PIs/PPIs (POs/PPOs) to be reused. The experimental results on larger ITC'99 benchmark circuits validate the effectiveness of the proposed method.

Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both shift and capture phases, which can cause circuits' reliability concerns during manufacturing test. This paper proposes a novel X-filling technique, namely “iFill”, to address the above issue, by analyzing the impact ofX-bitson switching activities of the circuit nodes in the two different phases. In addition, different from prior$X$-filling methods for shift-power reduction that can only reduce shift-in power, our method is able to cut down power consumptions in both shift-in and shift-out processes. Experimental results on benchmark circuits show that the proposed technique can guarantee the power safety in both shift and capture phases during at-speed scan-based testing.

Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-filling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT’s average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS’89 benchmark circuits show the effectiveness of the proposed methodology.

In scan-based tests, power consumptions in both shift and capture phases may be significantly higher than that in normal mode, which threatens circuits' reliability during manufacturing test. In this paper, by analyzing the impact of X-bits on circuit switching activities, we present an X-filling technique that can decrease both shift- and capture-power to guarantees the reliability of scan tests, called iFill. Moreover, different from prior work on X-filling for shift-power reduction which can only reduce shift-in power, iFill is able to decrease power consumptions during both shift-in and shift-out. Experimental results on ISCAS' 89 benchmark circuits show the effectiveness of the proposed technique.

Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ldquodonpsilat-carerdquo bits can be exploited for test data compression and/or test power reduction. Prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together. In this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. Experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.

We proposed clustered random access scan (CRAS) architecture to reduce test data volume. CRAS makes use of the compatibility of the test stimuli to cluster the scan cells, and assigns every cluster a unique address. The compression ratio upper bound of CRAS is analyzed based on the random graph theory. Experimental results on ISCAS'89 benchmarks and two industry designs show that the proposed CRAS architecture can yield on average 67.3% reduction in test data volume, with reasonable area and routing overhead than scan design

Recently test power dissipation has become a more and more challenging issue. This paper proposes a technique to solve this problem through scan chain adjustment to eliminate unnecessary transitions in scan chains. An extended WTM (EWTM) metric is proposed to estimate dynamic power dissipation in circuit under test caused by transitions in test stimulus and response vectors. And the routing overhead of this methodology can be reduced through scan chain adjustment guided with our Distance of EWTM (DEWTM) metric. Experimental results on ISCAS'89 benchmarks circuits show that the proposed approach can reduce average power dissipation during scan test by 72.2% on average, with negligible routing overhead.