The purpose of a vectorizer is to perform program restructuring in order to exhibit the most efficiently exploitable forms of vector loops. This is guided by a suitable form of semantic analysis, Dependence Testing, which must be precise in order to fully exploit the architecture. Most studies reduce this phase to the application of a series of explicitly computable arithmetic criteria. In many cases, this will fail if the criteria cannot be computed numerically, and contain symbols which cannot be evaluated. This also makes the use of other information pertaining to these symbols difficult. It is shown here that it is possible to extract symbolic equations from some of the classical criteria, merge them with other symbolic knowledge about the program, and use the global system to decide the non-existence of a dependence. In the context of the VATIL vectorizer [17, 16], it is also shown possible to control the computation cost, and obtain a good overall efficiency.

Compile-time scheduling of vector activities on the Cray 2 is studied using a simplified model of the vector instruction stream. An approach based on experience with an array-processor microde scheduling by the authors is shown to be practical. It calls for a pass of loop scheduling followed by a pass of resource allocation. Actual benchmarks of the resulting code are shown, exhibiting speedups as large as 50% over the current CFT77 compiler. The results also give a novel perspective on vector chaining vs. nonchaining processor architectures.>

It is of interest to determine whether loosely coupled multiprocessors can be profitably used for the solution of larger numerical problems. We present here a performance evaluation of the gain obtained by solving partial differential equation systems on such an architecture. The experimental setting is an LSI 11 based multimicroprocessor system using a fiber optics local area network designed and implemented at Laboratoire de Recherche en Informatique, Université Paris-Sud. The paper includes a discussion of the numerical methods and of their implementation, a performance model of the parallel processing system, and measurements taken on the experimental system. The experimentally validated theoretical results confirm the interest of our approach based on performance models.